PWR_RESET was set to 0x80 but should be 0x01 for the ICM 42688-p. The bit at 0x80 in the register is reserved. At best, this was not reseting the device when requested, at worst it was creating undefined behavior / setting bits in other registers (maybe related to #4 ?)
CLOCK_SEL_PLL was meant to be selecting the PLL for gyro, which is the default. However, CLOCK_SEL_PLL was set as 0x01, which was clearing the bit for ACCEL_LP_CLK_SEL, thus selecting the lower quality Wake Up clock. Before this change, the accel was not returning 9.8 when sitting on the table, but rather a value around 7.
ACCEL_FS_SEL bits were backwards (as noted in the code).
With these changes I am now getting valid accel measurements.
PWR_RESET
was set to0x80
but should be0x01
for the ICM 42688-p. The bit at0x80
in the register is reserved. At best, this was not reseting the device when requested, at worst it was creating undefined behavior / setting bits in other registers (maybe related to #4 ?)CLOCK_SEL_PLL
was meant to be selecting the PLL for gyro, which is the default. However,CLOCK_SEL_PLL
was set as0x01
, which was clearing the bit forACCEL_LP_CLK_SEL
, thus selecting the lower quality Wake Up clock. Before this change, the accel was not returning 9.8 when sitting on the table, but rather a value around 7.With these changes I am now getting valid accel measurements.