egaudry
commented
2 years ago For the sake of gathering information, here are some abstract from the ARM technical reference paper referenced above:
A6.1 About the L1 memory system
The Neoverse V1 L1 memory system is designed to enhance core performance and save power.
The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB.
A6.1.1 L1 instruction-side memory system
The L1 instruction memory system has the following key features:
• Virtually Indexed, Physically Tagged (VIPT) 4-way set-associative L1 instruction cache, which
behaves as a Physically Indexed, Physically Tagged (PIPT) cache
• Fixed cache line length of 64 bytes
• Pseudo-LRU cache replacement policy
• 256-bit read interface from the L2 memory system
• Optional instruction cache hardware coherency
The Neoverse V1 core also has a Virtually Indexed, Virtually Tagged (VIVT) 4-way skewed-associative,
Macro-OP (MOP) cache, which behaves as a PIPT cache.
A6.1.2 L1 data-side memory system
The L1 data memory system has the following features:
• Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, Physically
Tagged (PIPT) 4-way set-associative L1 data cache
• Fixed cache line length of 64 bytes
• Pseudo-LRU cache replacement policy
• 512-bit write interface from the L2 memory system
• 512-bit read interface from the L2 memory system
• One 128-bit and two 256-bit read paths from the data L1 memory system to the datapath
• 256-bit write path from the datapath to the L1 memory systemA7.1 About the L2 memory system
The L2 memory subsystem consists of:
• An 8-way set associative L2 cache with a configurable size of 512KB or 1MB. Cache lines have a
fixed length of 64 bytes.
• ECC protection for all RAM structures except victim array.
• Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
• Configurable CHI interface to the DynamicIQ Shared Unit (DSU) or CHI compliant system with
support for a 256-bit data width.
• Dynamic biased replacement policy.
• Modified Exclusive Shared Invalid (MESI) coherency
xrq-phys
As a user running on a node based on neoverse-v1 design, I'd like to us the armsve kernels with a better performance level than the neon-based ones.
This issue is a follow' up of https://github.com/flame/blis/issues/613 and https://github.com/flame/blis/issues/612 where the question of using generic values for
was raised, as performance using armsve with d5146582b1f1bcdccefe23925d3b114d40cd7e31 was 25% of that when running with thunderx2 kernels.
As noted by @xrq-phys,
The data found here https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1 and https://developer.arm.com/documentation/101427/latest/ might help.