Open flaming-cl opened 3 years ago
我的做法是先看视频写简短的notes,在做lab前看slides补充notes,有空或者有什么不懂看discussion。现在pj2,pj3正在同时解决,以及开始做lab7之后的lab作业。
TLB 的 valid bits 应该全部归零
offset: log2_(页数) VPN 位数 = address 位数 - offset 位数
1)Read 2)处理 LRU:清零该 entry 的 LRU value (LRU 数值越大,越不常用),以及增加其他 entries 的 LRU 数值
TLB miss 了,处理办法: 1)拿取 Free Physical Pages 里的第一个地址生成映射 2)把 TLB 中的最不常用 entry 踢掉(碰到并列第一「最不常用」的,随便取一个 3)valid -> 1 4)更新 LRU
Write + TLB hit, 改 dirty 为 1 补充: 眼镜哥说 TLB miss 是 page fault,回看第一题,这哥们应该是说错了
Q1:Explain the process by which we turn a virtual address into a physical address for the very first access (emphasizing on TLB Misses and Page Faults). First, convert address reference into binary form so that virtual page number is first three bits and the rest is offset in the page. Second, TLB would check pages according to the page number. If no matching entry was found, then it results in TLB miss.Then seach the page number in page table. If the page not found or the page table entry for this virtual page number had a valid bit of 0, then a page fault occurs. Q2: Why does the physical address only have 2 bits for the PPN while the virtual address has 3 bits for the VPN? There was 8 pages in virtual memory and 4 page frames in physical memory. Page number is set to check the page.
1.[00,20,40,60,80,00,20,40,60,80]
Q3:Explain why there is a much higher percentage of TLB misses in this simulation TLB size is way smaller than physical memory size.
注:等看书后再补充修改
课刷到后半段,意识到没必要跟着 20fa 来刷课,20su 就可以了。一是因为 20su 把 61C 主要内容抽出来了,压缩过的课时更短、更省时间。二是因为,Garcia 虽然讲得不错,但他有时候为了把一个事解释清楚,举了挺多不必要的例子,也挺浪费时间
我觉得刷 61C 的一个好方法是
Pipelining 61C
datapath 可以 pipelining,刷课也可以 pipelining: proj1 (C programming) 和 proj2 (RISC-V) 几乎没有知识交叠的地方,完全可以同时学完。proj3 数字电路 (有些内容要以 RISC-V 为基础),再之后才是 cache, VM, I/O, threads 这些常见的知识介绍。掌握基本的数字电路知识,过完相关 lab,其实就可以开始 proj3 之后的学习。这样能加速不少
Virtual Memory
VM 这里要讲的内容不是很多,核心内容是 1)VMA 怎么转换到 PMA 2)怎么保证转换过程安全有效 有效:layered page table,TLB(page table分级了以后,查询某个 PMA,可能要 access PM好几次,这里怎么提升效率呢?加缓存!在CPU内部加一个TLB,把转换过的 PMA 存起来备用) 安全:虽然我们给所有程序制造了独占、无限享有内存空间的假象,但它们始终 share 一个物理内存,万一有不老实的程序想窃取别人的数据呢?我们提前防范:![Screen Shot 2021-06-06 at 7 58 20 AM](https://user-images.githubusercontent.com/51183663/120908623-901ec480-c69e-11eb-8efe-f9c180aa5a68.png)
VM from 61C
以上问题的答案—— Paged Memory
Page protection: Page Tables
操作系统
转换 VM 和 PM
Please note: VPN and PPN share the same page size and page offset
小练习
Steps for locating a physical address
from VM address to PM address
Protection Between Processes
Page table 应该放在哪——主存
Cache 太小,Disc 太慢,同时用上 PT base register,用于找到当前 Page table 的物理地址
Page Table 不是线性的,是树状的(或者加cache)
假设某个 page table 只用到了第一个 page,后面的都用不到,那么就没必要去 load 一整个 page table。 但加 layers 也会导致更多的 PM access,这样降低了效率
解决办法 TLB
Please note: TLB 存的不是 memory 数据,而是 VPN 到 PPN 的映射 Translation Lookaside Buffers (TLB) Address translation is very expensive! In a single-level page table, each reference becomes two memory accesses In a two-level page table, each reference becomes three memory accesses Solution: Cache some translations in TLB TLB hit→Single-Cycle Translation TLB miss →Page-Table Walk to refill
TLB designs
Typically 32-128 entries, usually fully associative Each entry maps a large page, hence less spatial locality across pages more likely that two entries conflict Sometimes larger TLBs(256-512 entries) are 4-8 way set-associative Larger systems sometimes have multi-level (L1 and L2) TLBs Random or FIFO replacement policy “TLB Reach”: Size of largest virtual address space that can be simultaneously mapped by TLB
Which should we check first: Cache or TLB?
Can cache hold requested data if corresponding page is not in physical memory? No With TLB first, does cache receive VA or PA? Where Are TLBs Located? PA
![Screen Shot 2021-06-05 at 11 26 25 PM](https://user-images.githubusercontent.com/51183663/120896770-7efd9580-c655-11eb-9c97-c98498108ba8.png)
content switching
Context switch:Changing of internal state of processor (switching between processes) Save register values (and PC) and change value in Supervisor Page Table Base register (SPTBR) What happens to the TLB? Current entries are for different process Set all entries to invalid on context switchReview: Context Switching