"Dead" components

[richardabendroth]

Sometimes, components become "dead". They just don't work anymore. It's hard to reproduce. If the component is deleted and a new one is inserted instead, it works again. It might not even be the component but the net behind it that doesn't propagate.

[flandreas]

@richardabendroth Thank you for reporting this.

Do you have the feeling that it could be related with undo/redo? I guess that the problem persist, once it has occurred, when you save and reload the circuit. May I ask you to send me your project and the log file when the problem occurs the next time? This would be of great help to track down the root cause of the problem.

[richardabendroth]

Hey Andreas, I've not used undo/redo. It happened during connecting/reconnecting wires to the net behind it I think. I will certainly make a copy of the circuit when it happens the next time 😊

[flandreas]

@richardabendroth I am able to reproduce an instance of this problem by playing with the project you've uploaded in #583. It occurs in the version from 16.6.23, 1:36:40 in the main circuit. I can now analyse this.

[richardabendroth]

Nice!

[flandreas]

@richardabendroth I found out that the reason why the AND gate is dead is that the upper incoming wire (the one selected in the screenshot below) is connected with the AND on the view level, but not connected on the model layer. Therefore, input port 1 of the AND gate is always Z, and the AND gate produces 0 instead of the expected 1.

I now need to find the operation in the code that produces this model inconsistency.

I know it's a lot to ask, but do you by any chance remember how this wire came into existence? I see from the project history that you've designed the entire block with CNT, DEC and the pulse generators at the left side of the circuit, and then moved it in and connected the parts. Was copy/paste involved? Undo/redo?

It's okay if you can't remember, I'm just trying to reduce the amount of areas I have to inspect while searching for the bug.

[richardabendroth]

It's quite likely that I've used copy&paste. I tend to pick a component from the library when I need it the first time. For any additional component of the same type I tend to use copy&paste instead of picking it from the library because that is much faster. But I cannot remember if in this case the AND gate was a copy or picked from the library. But the probability of it originating from a copy&paste operation is quite high.

[flandreas]

@richardabendroth I'm currently focusing on finding the cause of this severe bug.

• Identify possible cause hypothesis
• Implement diagnostics for the various hypothesis
• A new feature that let the user export the entire system state for uploading to a GitHub issue and later analysis