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flandreas / antares

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VHDL: Cannot export standard lib circuits with unconnected outputs #676

Closed wmurbina closed 10 months ago

wmurbina commented 11 months ago

VHDL bugs. When I try to export a circuit with a register to VHDL, I get the following error. This is because in the flip-flop D Q' is not connected.

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flandreas commented 11 months ago

@wmurbina Thank you for reporting this.

The restriction to all pins being connected is intentional in VHDL export. However, I wasn't aware that the standard library has circuits with unconnected outputs. I have to think about how to deal with this..

flandreas commented 10 months ago

Relaxed restriction to "unconnected input pins" instead of "unconnected pins". Unconnected output pins are now allowed.