Error when exporting VHDL with an invalid test bench script

flandreas / antares

Digital circuit learning platform

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Closed flandreas closed 6 months ago

flandreas commented 7 months ago

Scenario

Circuit with a test case
The test case is invalid (e.g. references a pin that doesn't exist in the circuit any more)
Export to VHDL, testcase for test bench creation selected => Unexpected error

The VHDL exported should catch this situation and display a specific error msg such as "Test bench script is invalid".