If a circuit contains rectangles of style "Subsystem" (the ones with the dashed border), and you export the circuit as SVG, the subsystem rectangles are missing.
This is because "Subsystem" styles are forced to the background by application logic operating on the view level, not on the document level, but SVG generation operates on the document level.
If a circuit contains rectangles of style "Subsystem" (the ones with the dashed border), and you export the circuit as SVG, the subsystem rectangles are missing.
This is because "Subsystem" styles are forced to the background by application logic operating on the view level, not on the document level, but SVG generation operates on the document level.