Automatic Register Discovery

[riesentoaster]

• Goal: Automatically discover registers and allow the analyst to select them from a list instead of having to enter them manually.
• Ghidra's ProgramContext has a list of all registers.
• This list is way bigger than expected and contains a lot of irrelevant registers with no good way of filtering out the useful ones that an analyst would actually want to provide information for (see below).
• Based on this, it is probably easier for the analyst to enter the register names manually.
• If in the future filtering the list would be possible this issue might be reconsidered.

Dump:

[Name], [Description], [Name of AddressSpace], [Name of BaseRegister], [TypeFlags]
r0, null, register, r0, 0
r1, null, register, r1, 0
r2, null, register, r2, 0
r3, null, register, r3, 0
r4, null, register, r4, 0
r5, null, register, r5, 0
r6, null, register, r6, 0
r7, null, register, r7, 0
r8, null, register, r8, 0
r9, null, register, r9, 0
r10, null, register, r10, 0
r11, null, register, r11, 0
r12, null, register, r12, 0
sp, null, register, sp, 0
lr, null, register, lr, 0
pc, null, register, pc, 4
NG, null, register, NG, 0
ZR, null, register, ZR, 0
CY, null, register, CY, 0
OV, null, register, OV, 0
tmpNG, null, register, tmpNG, 0
tmpZR, null, register, tmpZR, 0
tmpCY, null, register, tmpCY, 0
tmpOV, null, register, tmpOV, 0
shift_carry, null, register, shift_carry, 0
TB, null, register, TB, 0
Q, null, register, Q, 0
GE1, null, register, GE1, 0
GE2, null, register, GE2, 0
GE3, null, register, GE3, 0
GE4, null, register, GE4, 0
cpsr, null, register, cpsr, 0
spsr, null, register, spsr, 0
mult_addr, null, register, mult_addr, 0
r14_svc, null, register, r14_svc, 0
r13_svc, null, register, r13_svc, 0
spsr_svc, null, register, spsr_svc, 0
mult_dat8, null, register, mult_dat16, 0
mult_dat16, null, register, mult_dat16, 0
fpsr, null, register, fpsr, 0
ISAModeSwitch, null, register, fpsid, 0
fpsid, null, register, fpsid, 0
fpscr, null, register, fpscr, 0
fpexc, null, register, fpexc, 0
mvfr0, null, register, mvfr0, 0
mvfr1, null, register, mvfr1, 0
fp0, null, register, fp0, 0
fp1, null, register, fp1, 0
fp2, null, register, fp2, 0
fp3, null, register, fp3, 0
fp4, null, register, fp4, 0
fp5, null, register, fp5, 0
fp6, null, register, fp6, 0
fp7, null, register, fp7, 0
cr0, null, register, cr0, 0
cr1, null, register, cr1, 0
cr2, null, register, cr2, 0
cr3, null, register, cr3, 0
cr4, null, register, cr4, 0
cr5, null, register, cr5, 0
cr6, null, register, cr6, 0
cr7, null, register, cr7, 0
cr8, null, register, cr8, 0
cr9, null, register, cr9, 0
cr10, null, register, cr10, 0
cr11, null, register, cr11, 0
cr12, null, register, cr12, 0
cr13, null, register, cr13, 0
cr14, null, register, cr14, 0
cr15, null, register, cr15, 0
s0, null, register, q0, 0
s1, null, register, q0, 0
s2, null, register, q0, 0
s3, null, register, q0, 0
s4, null, register, q1, 0
s5, null, register, q1, 0
s6, null, register, q1, 0
s7, null, register, q1, 0
s8, null, register, q2, 0
s9, null, register, q2, 0
s10, null, register, q2, 0
s11, null, register, q2, 0
s12, null, register, q3, 0
s13, null, register, q3, 0
s14, null, register, q3, 0
s15, null, register, q3, 0
s16, null, register, q4, 0
s17, null, register, q4, 0
s18, null, register, q4, 0
s19, null, register, q4, 0
s20, null, register, q5, 0
s21, null, register, q5, 0
s22, null, register, q5, 0
s23, null, register, q5, 0
s24, null, register, q6, 0
s25, null, register, q6, 0
s26, null, register, q6, 0
s27, null, register, q6, 0
s28, null, register, q7, 0
s29, null, register, q7, 0
s30, null, register, q7, 0
s31, null, register, q7, 0
d0, null, register, q0, 0
d1, null, register, q0, 0
d2, null, register, q1, 0
d3, null, register, q1, 0
d4, null, register, q2, 0
d5, null, register, q2, 0
d6, null, register, q3, 0
d7, null, register, q3, 0
d8, null, register, q4, 0
d9, null, register, q4, 0
d10, null, register, q5, 0
d11, null, register, q5, 0
d12, null, register, q6, 0
d13, null, register, q6, 0
d14, null, register, q7, 0
d15, null, register, q7, 0
d16, null, register, q8, 0
d17, null, register, q8, 0
d18, null, register, q9, 0
d19, null, register, q9, 0
d20, null, register, q10, 0
d21, null, register, q10, 0
d22, null, register, q11, 0
d23, null, register, q11, 0
d24, null, register, q12, 0
d25, null, register, q12, 0
d26, null, register, q13, 0
d27, null, register, q13, 0
d28, null, register, q14, 0
d29, null, register, q14, 0
d30, null, register, q15, 0
d31, null, register, q15, 0
q0, null, register, q0, 128
q1, null, register, q1, 128
q2, null, register, q2, 128
q3, null, register, q3, 128
q4, null, register, q4, 128
q5, null, register, q5, 128
q6, null, register, q6, 128
q7, null, register, q7, 128
q8, null, register, q8, 128
q9, null, register, q9, 128
q10, null, register, q10, 128
q11, null, register, q11, 128
q12, null, register, q12, 128
q13, null, register, q13, 128
q14, null, register, q14, 128
q15, null, register, q15, 128
contextreg, null, register, contextreg, 8
TMode, TMode, register, contextreg, 8
LRset, LRset, register, contextreg, 72
REToverride, REToverride, register, contextreg, 72
CALLoverride, CALLoverride, register, contextreg, 72
TEEMode, TEEMode, register, contextreg, 8
condit, condit, register, contextreg, 72
itmode, itmode, register, contextreg, 8
cond_full, cond_full, register, contextreg, 8
cond_base, cond_base, register, contextreg, 8
cond_true, cond_true, register, contextreg, 8
cond_shft, cond_shft, register, contextreg, 8
cond_mask, cond_mask, register, contextreg, 8
counter, counter, register, contextreg, 8
regNum, regNum, register, contextreg, 8
counter2, counter2, register, contextreg, 8
reg2Num, reg2Num, register, contextreg, 8
regInc, regInc, register, contextreg, 8
ARMcond, ARMcond, register, contextreg, 8
ARMcondCk, ARMcondCk, register, contextreg, 8