...each instruction payload starts the case step of its own opcode (with offset for ED and CB prefixes), so case steps 0..767 are occupied by the first payload clock cycle.
Each case step explicitly writes the next step (instead of step++).
Instructions that are longer than M1 put their additional case blocks starting at 768.
The remaining special case cycle blocks are grouped at the end.
This gets rid of the indirection 'optables' but results in a switch-case that's just as compact as now.
...each instruction payload starts the case step of its own opcode (with offset for ED and CB prefixes), so case steps 0..767 are occupied by the first payload clock cycle.
Each case step explicitly writes the next step (instead of step++).
Instructions that are longer than M1 put their additional case blocks starting at 768.
The remaining special case cycle blocks are grouped at the end.
This gets rid of the indirection 'optables' but results in a switch-case that's just as compact as now.