In DD+CB or FD+CB instructions (e.g. SET 1,(IX+1)) the disassembly in the tracelog and timing winow doesn't detect the end of the instruction and "leaks" into the next instrucion.
Probably related to the "fake" opcode fetch machine cycle in those instructions (the opcode after the DD+DB prefixes is loaded with a regular memory read machine cycle).
In DD+CB or FD+CB instructions (e.g.
SET 1,(IX+1)) the disassembly in the tracelog and timing winow doesn't detect the end of the instruction and "leaks" into the next instrucion.Probably related to the "fake" opcode fetch machine cycle in those instructions (the opcode after the DD+DB prefixes is loaded with a regular memory read machine cycle).