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fm4dd / gm-study-e1

EE education board for the GateMate FPGA evaluation board E1
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5V signal level conversion failure on connector J1 #3

Closed fm4dd closed 1 year ago

fm4dd commented 1 year ago

Per Texas Instruments application note SLV675B, the signal lines operated by the TI LSF204 level translation circuits (U2,U3,U4) need pull-up resistors. They need to be added in for high side (B-side), the low-side (A-side) is recommended for signal integrity. Need to verify and test the signal levels on J1 in detail. 5V power is present.

fm4dd commented 1 year ago

In further testing, the initial Texas Instruments LSF204 IC is not suitable for the application design. I successfully tested Texas Instruments TXB0104 IC's instead, having identical footprints allowing for simple type swap in the design. The TCB0104 has been validated through the PMOD-CharLCD board.

Side note: Many character LCD's only need the 5V for power, while their data lines operating on signal levels well below 3V and don't necessarily need the signal shifting to 5V. Adding this function is still a good way for me to validate such a design because LCD pin headers are versatile, and easy to be used as generic ports e.g. for breadboard expansion.