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forsyde / IDeSyDe

Design space identification and exploration
https://forsyde.github.io/IDeSyDe
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Non-issue, but system specifications for PL exploration #31

Closed BeethovenKodar closed 6 months ago

BeethovenKodar commented 6 months ago

Platform: MPSoC_Intermediate.txt

Application: ToySDF_Intermediate.txt

Rename the file extensions to .fiodl and you should be all set!

Rojods commented 6 months ago

Thanks! Will try out the files soon.

Rojods commented 6 months ago

Is it intentional that the Cores in the MPSoC have TDMAs schedulers? It could have been my bad explanation in some of our physical meetings!

If you wanted the cores to be "bare-metal" in the sense that @ingo-sander usually means, the correct trait is SuperLoopRuntime.

I am asking because _it is perfectly possible to account for TDMA, but there won't be any schedulers in the final result, only time-slots which will determine how the CPU is switching between processes.

For the moment, I will assume for simplicity that you meant SuperLoopRuntimes and act accordingly.

BeethovenKodar commented 6 months ago

Yeah I just picked some scheduler that I found in some demo file I believe. This was a long time ago, but sure go for the SuperLoopRuntimes!

BeethovenKodar commented 6 months ago

@Rojods Made some slight changes to the files. They use SuperLoopRuntime by default and one of the actors is hw mappable onto two possible FPGAs to enable more options in the exploration. This exact input is explored by the current IDeSyDe develop branch successfully. However, you said that the PL input specifications got a bid from the new MiniZinc explorer, but I don't see that and instead, Jenetics handles the exploration. I may have misunderstood something though. MPSoC_Intermediate.txt ToySDF_Intermediate.txt

Rojods commented 6 months ago

Now this has been solved through offline conversations and fixing the examples!