search

forsyde / IDeSyDe

Design space identification and exploration
https://forsyde.github.io/IDeSyDe
4 stars 4 forks source link

One actor is mapped to two PEs #33

Closed BeethovenKodar closed 6 months ago

BeethovenKodar commented 6 months ago

When running the attached files, Actor 1 is mapped to both the FPGA and a CPU, while Actor 2 does not get mapped to anything. I believe this is a typo (it "is" one to each PE in the solution) somewhere deep inside, i.e. not during reverse identification. I checked run/explored and the json file states this inconsistency too.

Files: evaluatorsdf.txt mpsoc.txt

BeethovenKodar commented 6 months ago

Remember I can just say the test case failed in the report! :)

Rojods commented 6 months ago

With the latest develop commit (I did do fixes as today, 2024-05-21) I get the following edges in my reversed model:

  edge [] from "Actor_2" port "mappingHost" to "OCM" 
  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "OCM" port "contained" to "Actor_2" 
  edge [] from "Actor_1" port "mappingHost" to "OCM" 
  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "OCM" port "contained" to "Actor_1" 
  edge [] from "CH_Actor_1_Actor_2" port "mappingHost" to "OCM" 
  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "OCM" port "contained" to "CH_Actor_1_Actor_2" 
  edge [] from "Actor_2" port "runtimeHost" to "RPU_C0_Scheduler" 
  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "RPU_C0_Scheduler" port "contained" to "Actor_2" 
  edge [] from "Actor_2" port "hostLogicProgrammableModule" to "FPGA" 
  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "FPGA" port "contained" to "Actor_2"

which I believe is correct now? There is one actor going to the scheduler and one going to the PLA! Can you pull the latest changes and test in your box, pllzzz :).

BeethovenKodar commented 6 months ago

Actually, I misread your output. See, "Actor 2" is going to both listed PEs, and "Actor 1" is only covered for the memory mapping. We have the same (prob incorrect) result.

Rojods commented 6 months ago

We have just solved it with the lastest develop branch! Seemingly.