VHDL Backend: Support FSVec and Tuple primitives - Githubissues

forsyde / forsyde-deep

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VHDL Backend: Support FSVec and Tuple primitives #13

Open HWoidt opened 8 years ago

HWoidt commented 8 years ago

Issue by HWoidt Saturday Jul 11, 2015 at 13:03 GMT Originally opened as https://gits-15.sys.kth.se/ingo/forsyde-deep/issues/13

Reported by alfonso....@gmail.com, Apr 24, 2008

Support for translation of FSVec and Tuple primitives:

Higher order functions (AbstExt.psi, FSVec.foldr, FSVec.map ...)
Functions using nested vectors (FSVec.concat, FSVec.group)
FSVec.length (Int is unfortunately system dependent)