forsyde / forsyde-deep

Other
1 stars 2 forks source link

Improve support for Case expressions in the VHDL backend #15

Open HWoidt opened 8 years ago

HWoidt commented 8 years ago

Issue by HWoidt Saturday Jul 11, 2015 at 13:04 GMT Originally opened as https://gits-15.sys.kth.se/ingo/forsyde-deep/issues/15


Reported by alfonso....@gmail.com, May 16, 2008

Currently, the VHDL backend is only able to translate naive case expressions. There is no support pattern-matching with tuples AbsExt expresions.