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foss-for-synopsys-dwc-arc-processors / qemu

QEMU port for ARCv2 Processors
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FPUv2: Implemented fpuv2 functionality #207

Closed BrunoASMauricio closed 1 year ago

BrunoASMauricio commented 1 year ago

This Pull Request implements fpuv2 functionality via helpers, just like fpuv3.

In doing so, a few changes were done besides fpu.

This is a single PR because:

  1. The changes not directly related to fpu are small and dont affect non-fpuv2 functionality
  2. If separated in PRs, their inclusion would need to be in a specific sequence because fpuv2 functionality depends on them.

The reasoning for each change is as follows:

DSP collisions

Some fpuv2 instructions collide with DSP instructions. Since the decoder currently can't disable any specific extension, removed all DSP instructions (which aren't planned for implementation either).

Shared functionality with v3

Fpuv2 shares functionality with Fpuv3. This general code was placed in fpu.c/h to be used by both

Mnemonic collisions

Some instructions between fpuv3 and fpuv2 have the same name but different amount of arguments (FSMADD, FSMSUB, FDMADD, FDMSUB).

This leads to problematic decoder behavior.

Solution is to use different mnemonics internally (append v2 to the mnemonics).

v3 adapters

As with some of the MPY instructions, some fpuv2 instructions behave exactly as their v3 counterparts.

Following the same logic as was used for MPY, created a couple of defines that perform the "interface" between the 32 bit instruction and the 64 bit helper.

This interface will always be necessary, via macro or not, as these operations themselves are 64 bit in nature.

kolerov commented 1 year ago

@BrunoASMauricio Do I understand right that fpu-helper.c is for ARCv3 targets and fpuv2-helper.c is for ARCv2 targets? I think such names don't fit in our nameing conventions. We have *-v2 and *-v3 files and these helper files may be confusing.

kolerov commented 1 year ago

@BrunoASMauricio Can you please explain how is FPU for QEMU is verified? I executed random FP test suites and they worked fine. Also, I compiled GLPK (it relies on FP heavily) and executed a bunch of examples and it also worked fine with the same results as on host machine.

BrunoASMauricio commented 1 year ago

@kolerov these changes were tested with two separate testsuites (compiled to run with all fpu instructions available). First running the glibc math tests, which test sine/cosine/type conversions and other such operations which very heavily rely on these changes. Second, an Ieee 754 compliance checker that I ported a while ago to ARC, and tests the exact bits expected by the standard for several operations. If you want more information on this last one, please pm me or contact @claziss All tests passed with success.

kolerov commented 1 year ago

@kolerov these changes were tested with two separate testsuites (compiled to run with all fpu instructions available). First running the glibc math tests, which test sine/cosine/type conversions and other such operations which very heavily rely on these changes. Second, an Ieee 754 compliance checker that I ported a while ago to ARC, and tests the exact bits expected by the standard for several operations. If you want more information on this last one, please pm me or contact @claziss All tests passed with success.

Can you please add a comprehensive information about it in QEMU Wiki?

Also, I see that there is no a getter for FPU_BUILD register. I would suggest to add. Note, that it has a different format for ARCv2 and ARCv3.

BrunoASMauricio commented 1 year ago

Hello @kolerov ! I have added the build register getter, and reran the glibc tests to make sure everything is still ok. Please check it out! I don't quite understand exactly what you want me to add to the QEMU wiki. Glibc tests are the same as stated there but with fpu flag. If it is about the IEEE checker, please discuss with @claziss how to refer to it since there is no official repository.

kolerov commented 1 year ago

@BrunoASMauricio LGTM. And the final question - are half-precision instructions (FH2S and FS2H) going to be implemented? Is it critical?

claziss commented 1 year ago

@BrunoASMauricio LGTM. And the final question - are half-precision instructions (FH2S and FS2H) going to be implemented? Is it critical?

I think those ones are not implemented at all. We should not care about them as GNU is concerned.

kolerov commented 1 year ago

@BrunoASMauricio LGTM. And the final question - are half-precision instructions (FH2S and FS2H) going to be implemented? Is it critical?

I think those ones are not implemented at all. We should not care about them as GNU is concerned.

@claziss @BrunoASMauricio So, it may be merged I suppose?