Open alex-etched opened 1 week ago
The root issue appears to result from GCC generating indirect calls by first loading the callee's address into a register before executing the branch-and-link, as it's handling a long call. This forces to be created of a pseudo register. The complication arises because, at this stage of compilation, no additional pseudo registers can be generated.
While the patch is being verified and tested, a possible temporary workaround is to modify the compilation options by excluding the memory model option.
arc64-elf-gcc app.cc -mcpu=hs6x -mfpu=none -m128 -mbbit -mbitscan -mbrcc -mcode-density --specs=nsim.specs
The following code will ICE the compiler:
Compile command + flags:
Version Info:
ccPL5RIM.out.zip