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fossi-foundation / wishbone

Specification of the Wishbone SoC Interconnect Architecture
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DDR Protocol for physical buses #21

Open jrmoserbaltimore opened 4 years ago

jrmoserbaltimore commented 4 years ago

I propose the next revision based on Wishbone B4 provide that a Wishbone Pipeline protocol MAY qualify all of certain signals as DDR to reduce pin count and increase transmission rate:

The following signals are always one full clock cycle (transaction):

The CYC signal asserts and deasserts on rising edge. TGC is SDR and applies for the entire bus cycle.

Alternately, as Rule 3.45 prohibits asserting more than one of ACK, ERR, and RTY simultaneously, it is possible to reduce those to a single signal at DDR:

Altogether this allows 29 pins plus CLK and RST for a 16-bit ADDR and DAT bus with 8-bit granularity, rather than 54 pins.

jrmoserbaltimore commented 4 years ago

As an example, I may describe a bus:

This bus carries 24 signals:

  • CYC
  • STB
  • STALL
  • ADDR[8]
  • DAT_IO[8]
  • SEL
  • TGC
  • ACK_ERR_RTY
  • CLK (generated)
  • RST (generated)

The bus is Wishbone DDR, and delivers ADDR, DAT_IO, SEL, and ACK_ERR_RTY on the rising and falling clock edges. All other signals are rising edge. A transaction is one full clock cycle.

The address and data buses are 16 bits transferred per transaction, 8 on each of the rising and falling clock edges. DAT_IO is multiplexed. DAT and ADDR are little-endian; SEL and ACK_ERR_RTY are serial from MSB to LSB.

At the beginning of each bus cycle, the Initiator sends ADDR and DAT_IO as a 32-bit page selector, selecting a 128KiB page of 16-bit words. For this it receives an ACK, ERR, or RTY as detailed in the appropriate section of the datasheet. Subsequent transactions address 16-bit words within the opened 65,536-entry page.

When TGC=0, the bus cycle is a read cycle. The Target sends DAT_IO=0 on the first ACK; subsequent transactions qualify DAT_IO with ACK_ERR_RTY as described in the appropriate section of the datasheet. The Initiator does not drive DAT_IO during a read cycle except for the first transaction to page-select.

When TGC=1, the bus cycle is a write cycle. The Target does not drive DAT_IO during a write cycle.

The bus described above can address 512 TiB. To address 128GiB of 16-bit words would usually require 36 ADDR and two sets of 16 DAT lines, plus CYC, STB, STALL, 2 SEL, ACK, WE, CLK, RST, a total 77 signal lines (79 withRTYandERR`, which is all the I/O lines on a SAM4S µC). This bus requires 24 lines and is appropriate for high-speed transactions, for example to use a µC's MCI controller to read SD cards at 40MiB/s or to use the µC as a HyperRAM controller (such a µC may forego 128KiB or more of internal SRAM in favor of a small scratchpad or cache to save on cost, allowing the use of a $3 8MiB HyperRAM module and providing DMA via a compact Wishbone bus; the bus described can operate at the full speed of HyperRAM).

A 332Mbit/s bus vastly outclasses SPI.