Open jrmoserbaltimore opened 4 years ago
As an example, I may describe a bus:
This bus carries 24 signals:
- CYC
- STB
- STALL
- ADDR[8]
- DAT_IO[8]
- SEL
- TGC
- ACK_ERR_RTY
- CLK (generated)
- RST (generated)
The bus is Wishbone DDR, and delivers
ADDR
,DAT_IO
,SEL
, andACK_ERR_RTY
on the rising and falling clock edges. All other signals are rising edge. A transaction is one full clock cycle.The address and data buses are 16 bits transferred per transaction, 8 on each of the rising and falling clock edges. DAT_IO is multiplexed.
DAT
andADDR
are little-endian;SEL
andACK_ERR_RTY
are serial from MSB to LSB.At the beginning of each bus cycle, the Initiator sends
ADDR
andDAT_IO
as a 32-bit page selector, selecting a 128KiB page of 16-bit words. For this it receives anACK
,ERR
, orRTY
as detailed in the appropriate section of the datasheet. Subsequent transactions address 16-bit words within the opened 65,536-entry page.When
TGC=0
, the bus cycle is a read cycle. The Target sendsDAT_IO=0
on the firstACK
; subsequent transactions qualifyDAT_IO
withACK_ERR_RTY
as described in the appropriate section of the datasheet. The Initiator does not driveDAT_IO
during a read cycle except for the first transaction to page-select.When
TGC=1
, the bus cycle is a write cycle. The Target does not driveDAT_IO
during a write cycle.
The bus described above can address 512 TiB. To address 128GiB of 16-bit words would usually require 36 ADDR
and two sets of 16 DAT
lines, plus CYC
, STB
, STALL
, 2 SEL
, ACK
, WE
, CLK
, RST, a total 77 signal lines (79 with
RTYand
ERR`, which is all the I/O lines on a SAM4S µC). This bus requires 24 lines and is appropriate for high-speed transactions, for example to use a µC's MCI controller to read SD cards at 40MiB/s or to use the µC as a HyperRAM controller (such a µC may forego 128KiB or more of internal SRAM in favor of a small scratchpad or cache to save on cost, allowing the use of a $3 8MiB HyperRAM module and providing DMA via a compact Wishbone bus; the bus described can operate at the full speed of HyperRAM).
A 332Mbit/s bus vastly outclasses SPI.
I propose the next revision based on Wishbone B4 provide that a Wishbone Pipeline protocol MAY qualify all of certain signals as DDR to reduce pin count and increase transmission rate:
ADDR
- An 8-signalADDR
bus transfers 16 bits ofADDR
in one clock cycle (transaction)DAT_I
,DAT_O
- An 8-signalDAT
transfers 16 bits in one transactionSEL
- Half as many signals for the same number of SEL bitsTGD
TGA
The following signals are always one full clock cycle (transaction):
STB
STALL
WE
ACK
ERR
RTY
LOCK
The
CYC
signal asserts and deasserts on rising edge.TGC
is SDR and applies for the entire bus cycle.Alternately, as Rule 3.45 prohibits asserting more than one of
ACK
,ERR
, andRTY
simultaneously, it is possible to reduce those to a single signal at DDR:00
= nothing11
=ACK
01
=ERR
10
=RTY
Altogether this allows 29 pins plus
CLK
andRST
for a 16-bitADDR
andDAT
bus with 8-bit granularity, rather than 54 pins.