Simple gain documentation

[fe-tdavis]

Added figures and READMEs for the simple gain models

[tvannoy]

A key feature of this model is that the processing only occurs on the rising edge of the valid signal.

Indeed, the simple gain model uses an enabled subsystem. If I recall correctly, this results in the generated code only being enabled while the valid signal is high, thus the computations all take place within a single clock cycle. However, our "vectorized" models, like the vector simple gain, are also synchronous with the rising edge of the valid signal because new data only gets latched in on the rising edge of valid. Although in the case of vectorized models, computations can (will?) happen on every clock cycle. @fe-wickham correct me if I'm wrong; it's been a while... so I could be not understanding something with all of the clock rate pipelining etc. that we sometimes have going on.

This comment is more just for my own clarification, as I don't really have any issue with the wording in these READMEs -- it's really just splitting hairs.