Looks like Xilinx must have changed the name of the PS reset block in the netlist. In order for this project to successfully build, you need to replace all instances of *rst_ps7_0_100M* with *rst_processing_system7_0_100M* in Vivado/src/bd/design_1.tcl.
Hi Jeff,
Looks like Xilinx must have changed the name of the PS reset block in the netlist. In order for this project to successfully build, you need to replace all instances of
*rst_ps7_0_100M*
with*rst_processing_system7_0_100M*
in Vivado/src/bd/design_1.tcl.