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fpgasystems / Coyote

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
MIT License
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Each completion queue contains 2-cycle burst valid signal #78

Open zhenhaohe opened 2 months ago

zhenhaohe commented 2 months ago

Hi all,

Recently I found a potential bug with the completion queue of Coyote. Each compeletion of the request comes with a 2-cycle burst valid signal instead of a 1-cycle valid.

maximilianheer commented 1 month ago

Hi @zhenhaohe or @quetric, can we maybe get a bit more context on this issue? Which scenario, which busses are we talking about? Do you maybe even have a screenshot of waveforms or something like this?

quetric commented 1 month ago

This bug is observed on the cq_wr bus. I don't have a screenshot of waveforms, but the context is that after a write request is issued on sq_wr, we are observing cq_wr for a completion. The bug is that instead of TVALID staying high for 1 cycle to signal a completion, it stays high for 2 consecutive cycles.

maximilianheer commented 1 month ago

Hi @quetric, thanks a lot for the clarification. We'll be looking into it.