the loop back user core issue

[ducdracaena]

I want to build a 100G tcp/ip server in fpga, so pc client can send data to server and server can loop back that data to pc client. I have changed the ipert core but that core is only receive. Could you please take a look at that code and let me know where is issue?

switch (serverFsmState)
{
case WAIT_PKG:
    if (!rxMetaData.empty() && !rxDataBuffer.empty())
    {
        rxMetaData.read();
        net_axis<WIDTH> receiveWord = rxDataBuffer.read();
        if (!receiveWord.last)
        {
            serverFsmState = CONSUME;
        }
    }
    break;
case CONSUME:
    if (!rxDataBuffer.empty())
    {
        receiveWord = rxDataBuffer.read();
        if (receiveWord.last)
        {
            serverFsmState = WRITE_PKG;
        }
    }
    break;
case WRITE_PKG:
{
    txDataBuffer.write(receiveWord);
    if (receiveWord.last)
    {
        serverFsmState = WAIT_PKG;
    }
}
    break;
}

Thank you, Duc