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fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells
https://systems.ethz.ch/fpga
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HARDWARE build error related to GTY. #14

Closed IshtiyaqueShaikh closed 1 year ago

IshtiyaqueShaikh commented 1 year ago

Hi, When I am trying to build hardware for the project I am getting below error:

ERROR: [VPL UTLZ-1] Resource utilization: GTYE4_CHANNEL over-utilized in Pblock pblock_dynamic_region (This design requires more GTYE4_CHANNEL cells than are available in Pblock 'pblock_dynamic_region'. This design requires 10 of such cell types but only 8 compatible sites are available in Pblock 'pblock_dynamic_region'. Please consider increasing the span of Pblock 'pblock_dynamic_region' or removing cells from it.)

I could not find any useful information on the web, any pointer would be helpful.

Thanks and regards, Ishtiyaque Shaikh

IshtiyaqueShaikh commented 1 year ago

this issue is not present when build using the scripts supplied in the project. Initially i tried to create project manually and all custization of cmac_usplus 100G ethernet system IP is not done hence this problem came.