search

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells
https://systems.ethz.ch/fpga
177 stars 72 forks source link

Do we need different cmac_usplus settings if testing in 10G network. #16

Open IshtiyaqueShaikh opened 1 year ago

IshtiyaqueShaikh commented 1 year ago

Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF

Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ?

Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ?

lizajoseph commented 5 months ago

Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF

Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ?

Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ?

Hi [IshtiyaqueShaikh],

Where you able to successfully port this design to 10G Ethernet IP subsystem?

Thanks, Liza

IshtiyaqueShaikh commented 5 months ago

100g stack will not work with 10g ethernet. I do not have 100g network so cmac ip did not come up.

Regards, Ishtiyaque

On Thu, 14 Mar, 2024, 3:49 pm lizajoseph, @.***> wrote:

Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF

Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ?

Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ?

Hi [IshtiyaqueShaikh],

Where you able to successfully port this design to 10G Ethernet IP subsystem?

Thanks, Liza

— Reply to this email directly, view it on GitHub https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP/issues/16#issuecomment-1997105733, or unsubscribe https://github.com/notifications/unsubscribe-auth/AKQHCRJBYJNFBQXFFWIYDX3YYF2UBAVCNFSM6AAAAAAZB45FCSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSOJXGEYDKNZTGM . You are receiving this because you authored the thread.Message ID: @.***>

lizajoseph commented 5 months ago

100g stack will not work with 10g ethernet. I do not have 100g network so cmac ip did not come up. Regards, Ishtiyaque … On Thu, 14 Mar, 2024, 3:49 pm lizajoseph, @.> wrote: Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ? Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ? Hi [IshtiyaqueShaikh], Where you able to successfully port this design to 10G Ethernet IP subsystem? Thanks, Liza — Reply to this email directly, view it on GitHub <#16 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AKQHCRJBYJNFBQXFFWIYDX3YYF2UBAVCNFSM6AAAAAAZB45FCSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSOJXGEYDKNZTGM . You are receiving this because you authored the thread.Message ID: @.>

Thanks for your response, where you able to generate the bitfile for this design targeting to Alveo u280 design ? I am getting errors as given below when I try to build this design targeting to u50 card.

ERROR: [VPL 8-11365] for the instance 'iperf_client' of module 'iperf_client_ip' declared at '/home/liza.joseph@CORP.FLOWEDGE.IN/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ip/ulp_iperf_krnl_1_0/src/iperf_client_ip/synth/iperf_client_ip.v:53', named port connection 'm_axis_close_connection_TVALID' does not exist [vi :296] ERROR: [VPL 8-11365] for the instance 'iperf_client' of module 'iperf_client_ip' declared at '/home/liza.joseph@CORP.FLOWEDGE.IN/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ip/ulp_iperf_krnl_1_0/src/iperf_client_ip/synth/iperf_client_ip.v:53', named port connection 'm_axis_close_connection_TREADY' does not exist [/home/liza.joseph@CORP.FLOWEDGE.IN/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/29bf/src/iperf_role.sv:297] ERROR: [VPL 8-11365] for the instance 'iperf_client' of module 'iperf_client_ip' declared at '/home/liza.joseph@CORP.FLOWEDGE.IN/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ip/ulp_iperf_krnl_1_0/src/iperf_client_ip/synth/iperf_client_ip.v:53', named port connection 'm_axis_close_connection_TDATA' does not exist [/home/liza.joseph@CORP.FLOWEDGE.IN/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/29bf/src/iperf_role.sv:298]

Thanks, Liza

IshtiyaqueShaikh commented 5 months ago

As per Xilinx support cmac will not work with 10g network. It means we can not make 100g stack working on 10g network. However we can build 10g toe on vivado 2022.2 with 10g ethernet ip. This will work on 10g network.

Regards Ishtiyaque

On Thu, 14 Mar, 2024, 3:49 pm lizajoseph, @.***> wrote:

Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF

Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ?

Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ?

Hi [IshtiyaqueShaikh],

Where you able to successfully port this design to 10G Ethernet IP subsystem?

Thanks, Liza

— Reply to this email directly, view it on GitHub https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP/issues/16#issuecomment-1997105733, or unsubscribe https://github.com/notifications/unsubscribe-auth/AKQHCRJBYJNFBQXFFWIYDX3YYF2UBAVCNFSM6AAAAAAZB45FCSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSOJXGEYDKNZTGM . You are receiving this because you authored the thread.Message ID: @.***>

lizajoseph commented 5 months ago

As per Xilinx support cmac will not work with 10g network. It means we can not make 100g stack working on 10g network. However we can build 10g toe on vivado 2022.2 with 10g ethernet ip. This will work on 10g network. Regards Ishtiyaque … On Thu, 14 Mar, 2024, 3:49 pm lizajoseph, @.> wrote: Hi, I have build the project on Vitis 2022.2 targeting Alveo280 board. However my network is 10G only. Do we need to change any setting in cmac_usplus 3.1 (100G Ethernet System IP) to make it working on 10G network. Currently I have put ILA on cmac_usplus rx side and I see following error status : stat_rx_internal_local_fault = 1 stat_rx_local_fault = 1 stat_rx_synced_err = FFFF Current IP setting is Mode=CAUI4, Line Rate=4X25.78G Should I change Mode to CAUI10 and Line Rate=10X10G ? Also how do we know if cmac GTY is constraint to ethernet port 0 or 1 of Alveo280 in the design ? Hi [IshtiyaqueShaikh], Where you able to successfully port this design to 10G Ethernet IP subsystem? Thanks, Liza — Reply to this email directly, view it on GitHub <#16 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AKQHCRJBYJNFBQXFFWIYDX3YYF2UBAVCNFSM6AAAAAAZB45FCSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSOJXGEYDKNZTGM . You are receiving this because you authored the thread.Message ID: @.> Hi Ishtiyaque, Thanks for your response. Do you have a 10G TOE with 10G ethernet IP working model targeting any Alveo card?

Thanks, Liza