search

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells
https://systems.ethz.ch/fpga
173 stars 71 forks source link

Error during creation of HLS IP cores #20

Open lizajoseph opened 4 months ago

lizajoseph commented 4 months ago

When I do “make all”, I seem to get the same error on HLS ip cores as seen below.

WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'axis_256_to_64_converter' to 'axis_256to_64_converter' is not allowed and is ignored. ERROR: [Coretcl 2-1134] No IP matching VLNV 'ethz.systems:hls:toe:1.6' was found. Please check your repository configuration.

while executing

"source $path_to_pack_tcl/network_stack.tcl" (file "kernel/network_krnl/package_network_krnl.tcl" line 85)

while executing

"source -notrace ${package_tcl_path}" (file "scripts/gen_xo.tcl" line 53) INFO: [Common 17-206] Exiting Vivado at Thu Mar 14 15:29:41 2024... make: *** [config_rtl.mk:4: _x.hw.xilinx_u50_gen3x16_xdma_5_202210_1/network_krnl.xo] Error 1

Has anyone able to fix this issue?

Mishmeria commented 3 months ago

i have same issue. Are you fix this already? if fixed pls to me how to. thank you!