Whether the project support U50 theoretically?

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

https://systems.ethz.ch/fpga

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Whether the project support U50 theoretically? #4

Open IskandarZhang opened 3 years ago

IskandarZhang commented 3 years ago

I've spent weeks on porting the whole project to Alveo U50 but its still doesnt work. I'd like to know if there anybody who port it successfully and how? Best.

IskandarZhang commented 3 years ago

I suggest the bug is in 'post_sys_link.tcl' ERROR: [VPL 5-106] Arguments to the connect_bd_intf_net command cannot be empty. in which the code leads to error occurs in the .tcl file mentioned above, but i have no idea about why the provided file leads to the error.

lizajoseph commented 8 months ago

IskandarZhang

Hi, Where you able to target this design on Alveo u50 card?

Thanks, Liza