fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells
https://systems.ethz.ch/fpga
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Update cmac_krnl.sv #8

Open haiyang3-98 opened 2 years ago

haiyang3-98 commented 2 years ago

Don't know why you put 0 in sys_reset but clearly many logic and the cmac ip depend on this signal to be initialized