fpgasystems / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
BSD 3-Clause "New" or "Revised" License
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vcu118: ethernet_10g_ip is giving fault. #12

Closed IshtiyaqueShaikh closed 4 years ago

IshtiyaqueShaikh commented 4 years ago

We have loaded bit stream for TOE project on VCU118. ethernet_10g_ip is transmitting packet which can capture through the tcpdump on network. However when we tried to ping we do not see any activity on rx side of the ethernet_10g_ip. I have captured stat_rx_local_fault and stat_rx_internal_local_fault of ethernet_10g_ip using ILA. These stats are coming continuously high.

I will appreciate if we can get pointer to debug this issue further.

thanks and regards, Ishtiyaque Shaikh

dsidler commented 4 years ago

What is the frequency of the programmable clock used for the Ethernet core? it should be 156.25Mhz

IshtiyaqueShaikh commented 4 years ago

What is the frequency of the programmable clock used for the Ethernet core? it should be 156.25Mhz

It is constraint to 6.4ns (156.25Mhz) in xdc file. Do we need to make any changes in ethernet_10g_ip customization.

dsidler commented 4 years ago

The vcu118 has 4 programmable clocks, one of them is used to drive the Ethernet core. The clock is called Programmable User Clock 2, please check the VCU118 User Guid page 47.

IshtiyaqueShaikh commented 4 years ago

I have captured rx_core_clk, rx_clk_out and tx_clk_out of ethernet_10g_ip and they seems to be working. Checked using ILA.

dsidler commented 4 years ago

Can you tell me what the GT RefClk of the ethernet_10_ip module is?

IshtiyaqueShaikh commented 4 years ago

GT RefClk is 6.4ns (156MHz). Do we have a fpga network stack which uses 1G ethernet and not 10G. Basically we are not able to make QSFP connectivity working so thinking if we can use 1G ethernet.

IshtiyaqueShaikh commented 4 years ago

Hi Sidler, The current design is constraint to QSFP1. I would like to constraint to QSFP2 to see if works since i am not able to have rx working on QSFP1. I would like to know if changing below constraint are sufficient for changing QSFPs. set_property PACKAGE_PIN Y2 [get_ports {gt_rxp_in[0]}] set_property PACKAGE_PIN Y1 [get_ports {gt_rxn_in[0]}] set_property PACKAGE_PIN V7 [get_ports {gt_txp_out[0]}] set_property PACKAGE_PIN V6 [get_ports {gt_txn_out[0]}]

I tried using ethernet_10g_ip example design i found that if I use gt_loopback=0 then i see the stat_rx_local_fault etc. But if we use gt_loopback=1 or 2 the packet generator and loopback send packet to rx.

IshtiyaqueShaikh commented 4 years ago

The problem was with hardware QSFP1 port of the VCU118 board. We change constraint file to use QSFP2 port which fix this issue.

IshtiyaqueShaikh commented 4 years ago

closing the issue.