search

fpgasystems / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
BSD 3-Clause "New" or "Revised" License
699 stars 256 forks source link

Reason for AXI4-Stream register slices #16

Closed G33KatWork closed 4 years ago

G33KatWork commented 4 years ago

Hi,

I am currently reading the code of your network stack and want to port it to a Zynq 7100 board. Even though I have huge troubles building a complete project for one of the example boards, I think I got how most of this stuff works and I'm trying to build a Vivado block diagram to get some simple ARP, and ICMP going for now to iterate on with UDP and later TCP.

However, I don't know why there are AXI4-Stream register slices between a bunch of the cores. I don't see a clock domain crossing and as far as I can see, the slices don't contain any FIFOs, right? Could you please elaborate why the slices are necessary?

Thanks,

dsidler commented 4 years ago

Hi Andy,

The register slices were introduced to improve timing. It is possible that on your board this is not necessary.

David

G33KatWork commented 4 years ago

Oh, right, that makes sense. Thank you!