How to generate bitstream (wiki is outdated)

[lomotos10]

I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.

To generate the bitstream, the wiki says to run Vivado using create_vcu118_proj.tcl, which is now located in scripts instead of projects.

Even after manually modifying the script to satisfy the current repository (redirecting rtl to hdl, upgrading IP versions, etc.) the build outputs error at the following step:

# update_compile_order -fileset sources_1
# create_ip -name ip_handler -vendor ethz.systems -library hls -version 1.2 -module_name ip_handler_ip -dir $ip_dir/vu9p
ERROR: [Coretcl 2-1134] No IP matching VLNV 'ethz.systems:hls:ip_handler:1.2' was found. Please check your repository configuration.

It would be most helpful if there was an up-to-date method detailing how to generate the bitstream.

[wegul]

In your case, try change the vendor name to ethz.systems.fpga.

[HirunaVishwamith]

I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.

To generate the bitstream, the wiki says to run Vivado using create_vcu118_proj.tcl, which is now located in scripts instead of projects.

Even after manually modifying the script to satisfy the current repository (redirecting rtl to hdl, upgrading IP versions, etc.) the build outputs error at the following step:

# update_compile_order -fileset sources_1
# create_ip -name ip_handler -vendor ethz.systems -library hls -version 1.2 -module_name ip_handler_ip -dir $ip_dir/vu9p
ERROR: [Coretcl 2-1134] No IP matching VLNV 'ethz.systems:hls:ip_handler:1.2' was found. Please check your repository configuration.

It would be most helpful if there was an up-to-date method detailing how to generate the bitstream.

Could you kindly let me know if you have been able to generate the bitstream file? If so, could you please provide me with some instructions on how to do it?

[lizajoseph]

I am trying to generate the bitstream but I am hitting the same error, was anyone able to proceed further?

create_ip -name mac_ip_encode -vendor xilinx.labs -library hls -module_name mac_ip_encode_ip -dir $ip_dir/vu9p

ERROR: [Coretcl 2-1134] No IP matching VLNV 'xilinx.labs:hls:mac_ip_encode:*' was found. Please check your repository configuration.

Thanks, Liza

[lizajoseph]

In your case, try change the vendor name to ethz.systems.fpga.

I tried to change the vendor name from ethz.systems to ethz.systems.fpga, but getting the same issue

[HirunaVishwamith]

I think you should try this repo, "https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP" It uses the same repo "fpga-network-stack" and I was able to generate the bitstream using that repo

[lizajoseph]

I think you should try this repo, "https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP" It uses the same repo "fpga-network-stack" and I was able to generate the bitstream using that repo

Thank you for your response, Did you try testing the bitfile on hardware? I see that in this repo they are using a 100G Ethernet subsystem, whereas I want a 10G Ethernet subsystem so that I can test it on my hardware Alveo u50. Could you let me know which hardware platform have you targeted this design ?

Thanks, Liza

[HirunaVishwamith]

I implemented it on U250. I don't know if it works on U50.

Thanks, Hiruna

[lizajoseph]

I implemented it on U250. I don't know if it works on U50.

Thanks, Hiruna

Where you able to test the bitfile on U250 hardware?

[HirunaVishwamith]

I use XRT interface to program the bitstream on U250. You should follow these two videos.

• https://youtu.be/nvU2ZBnAaz4?si=Y2Mr1FXuQ4b4FYjQ
• https://www.xilinx.com/video/software/xilinx-xclbin-utility-introduction.html

[lizajoseph]

I use XRT interface to program the bitstream on U250. You should follow these two videos.

• https://youtu.be/nvU2ZBnAaz4?si=Y2Mr1FXuQ4b4FYjQ
• https://www.xilinx.com/video/software/xilinx-xclbin-utility-introduction.html

Okay, Thank you I did a git clone of this repo, the fpga-network-stack folder is empty https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP

[HirunaVishwamith]

Don't just download the clone use this command git clone --recurse-submodules https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP.git or git clone --recurse-submodules git@github.com:fpgasystems/Vitis_with_100Gbps_TCP-IP.git submodules needs to be downloaded.

[lizajoseph]

Don't just download the clone use this command git clone --recurse-submodules https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP.git or git clone --recurse-submodules git@github.com:fpgasystems/Vitis_with_100Gbps_TCP-IP.git submodules needs to be downloaded.

Yes, it works with your command. However when I do make ip, it uses the u55 platform as seen below, did you update the CMakeLists.txt in "hls" to u250 part? INFO: [HLS 200-1510] Running: open_solution xcu55c-fsvh2892-2L-e

[HirunaVishwamith]

Reclone the repo and run the following commands

mkdir build
cd build
cmake .. -DFDEV_NAME=u250 -DTCP_STACK_EN=1
make ip

If you are using U50 use that instead. Before you run the remaining codes generate a license file for 100G subsystem and properly install it to your system. Next run these commands. Include the platform file location in your system as the DEVICE attribute.

cd ../
make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u250_gen3x16_xdma_3_1_202020_1/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm USER_KRNL=iperf_krnl USER_KRNL_MODE=rtl NETH=4

Make sure to check whether the platform file is comparable with the Vitis HLS versions that you are running

[lizajoseph]

Reclone the repo and run the following commands

mkdir build
cd build
cmake .. -DFDEV_NAME=u250 -DTCP_STACK_EN=1
make ip

If you are using U50 use that instead. Before you run the remaining codes generate a license file for 100G subsystem and properly install it to your system. Next run these commands. Include the platform file location in your system as the DEVICE attribute.

cd ../
make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u250_gen3x16_xdma_3_1_202020_1/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm USER_KRNL=iperf_krnl USER_KRNL_MODE=rtl NETH=4

Make sure to check whether the platform file is comparable with the Vitis HLS versions that you are running

yes, I have the XRT and Vitis installed compatible with u50 card, when I do the "make all" I hit the following error which I was facing in this https://github.com/fpgasystems/fpga-network-stack Could you let me know how you resolved this issue?

ERROR: [Coretcl 2-1134] No IP matching VLNV 'ethz.systems.fpga:hls:toe:*' was found. Please check your repository configuration.

while executing

"source $path_to_pack_tcl/network_stack.tcl" (file "kernel/network_krnl/package_network_krnl.tcl" line 85)

while executing

"source -notrace ${package_tcl_path}" (file "scripts/gen_xo.tcl" line 53) INFO: [Common 17-206] Exiting Vivado at Thu Mar 14 12:57:52 2024... make: *** [config_rtl.mk:4: _x.hw.xilinx_u50_gen3x16_xdma_5_202210_1/network_krnl.xo] Error 1

[HirunaVishwamith]

I think they update their repo recently if you email me I'll share my files with you.

[lizajoseph]

I think they update their repo recently if you email me I'll share my files with you.

Thank you for your help This is my email id: liza.joseph@flowedge.in

[KaiLv16]

I think they update their repo recently if you email me I'll share my files with you.

@lizajoseph Hi, I'm currently working on reproducing this project on U50 too. I'm wondering if you could share the files with me. My email is kevinlevis60@gmail.com. Thank you very much!

[lizajoseph]

I think they update their repo recently if you email me I'll share my files with you.

@lizajoseph Hi, I'm currently working on reproducing this project on U50 too. I'm wondering if you could share the files with me. My email is kevinlevis60@gmail.com. Thank you very much!

Hi, I was not able to map this project to u50.

[zjb2023]

I think they update their repo recently if you email me I'll share my files with you.

@lizajoseph Hi, I'm currently working on reproducing this project on U50 too. I'm wondering if you could share the files with me. My email is kevinlevis60@gmail.com. Thank you very much!

I'm currently working on reproducing this project on U200.I'm wondering if you could share the files with me. My email is zhijiabin@zhejianglab.com Thank you very much!