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fpgasystems / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
BSD 3-Clause "New" or "Revised" License
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There may be a bug in the txEngMemAccessBreakdown() module? #31

Open LittleBlackLiu opened 1 year ago

LittleBlackLiu commented 1 year ago

Bug situation: In my test, the APP established multiple connections through the TCP interface. When retransmission and address loopback occur, the retransmission data is abnormal. Expected behavior: When retransmission and address wrapping occur at the same time, TCP should issue two read commands to DDR. The start address of the second read command should be {SESSION_ID,{WINDOW_BITS{1’b0}}. Actual behavior: According to line 1489 of the txEngMemAccessBreakdown() module in _hls/toe/tx_engine/txengine.cpp, the start address for the second read command is incorrectly set to 0. outputMemAccess.write(mmCmd(0, cmd.bbt - lengthFirstAccess)); Possible modifications:

ap_uint<32> pkgAddr;
pkgAddr(31, 30) = cmd.saddr(31, 30);
pkgAddr(29, WINDOW_BITS) = cmd.saddr(29, WINDOW_BITS);
pkgAddr(WINDOW_BITS-1, 0) = 0;
outputMemAccess.write(mmCmd(pkgAddr, cmd.bbt - lengthFirstAccess));
GraceDouX commented 9 months ago

Hi,Can you explain how to perform TCP tests and how to find TCP port numbers?