Report Timing summary showing -ve slacks for tcp toe.

[IshtiyaqueShaikh]

I have added timing constraint as following: dclock=8ns refclock=6.4ns.

Then i run synthesis and Report Timing Summary. I have observed following : Setup:

Worst Negative Slack: -5.6ns

Hold:

Worst Hold Slack=-0.349ns

Pulse Width:

Worst Pulse Width Slack= -0.02ns

My understanding is that all above values should be positive for meeting timing constraint before running on hardware. I do not have hardware VCU118 now but i will get in future. I want to make sure that design work on real hardware without any surprises.

Please comments/suggest.

Thanks and regards, Ishtiyaque ishaikh101274@gmail.com

[dsidler]

Are you looking at the report after synthesis or implementation?

[IshtiyaqueShaikh]

I have generated timing report after synthesis.

[dsidler]

This is just an estimation and not accurate. Only the timing report after place and route should be considered.

[IshtiyaqueShaikh]

So we need to run timing analysis after running implementation ? Do you remember if the timing report has any slack after synthesis/implementation ?