fpgasystems / spooNN

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
GNU Affero General Public License v3.0
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add halfsqueezenet_0 IP to a hdmi overlay? #4

Closed ghost closed 6 years ago

ghost commented 6 years ago

Hi,

Create learning repository!

Thanks to your detailed REAM.ME, I have rebuilt the halfsqueezenet hw. And I have a hdmi overlay by removing some many components of thebase overlay.

What I'm trying to do is that add the halfsqueezenet_0 IP to the hdmi overlay, so it's a live demo. But adding the halfsqueezenet_0 IP and the AXI DIrect Memory Access IP, I got some error.

Can you give me some advises about how you constructed your original block diagram, (because we rebuild your overlay according to the procsys.tcl which wasn't written by human~ ) and which IP I should add to get a live halfsqueezenet overlay?

Thank you.

kaankara commented 6 years ago
ghost commented 6 years ago

Thank you for your quick reply! Your professional repository and answer really help me a lot, and I have made a live demo with your kind suggestion.

The other thing that makes me wonder is the C++ code used for hls which looks like specific for hls and combines the hwand sw. What if I what to write my own layers and top function?

Can you give me some advises about your coding philosophy about c++ for hls and how you write them for hls?

Thank you.

kaankara commented 6 years ago

If you want to touch the HLS library and write your own layers etc., I recommend getting familiar with Vivado HLS first. You can follow the following tutorial as a starting point: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug871-vivado-high-level-synthesis-tutorial.pdf

I am closing this thread. If you have any specific questions later on, don't hesitate to contact me via email. I would be happy to help.

ghost commented 6 years ago

Thank you very much.@kaankara