Closed ghost closed 6 years ago
About how the block design is created, you can use this document as a reference: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_3/ug994-vivado-ip-subsystems.pdf
About modifying the existing block design: After using procsys.tcl to create the block design, you can make changes on it in Vivado. You don't need to start from scratch.
About combining HDMI IP and halfsqueezenet: I am not sure that design would fit. My guess is that it won't. If you want to have a live demo, the simple way is to just connect a USB camera to the PYNQ. The frames can be captured by the CPU (this is very easy to do in Python) and can be passed onto the FPGA to do the object detection. This way, you don't have to change the hardware side at all.
Thank you for your quick reply! Your professional repository and answer really help me a lot, and I have made a live demo with your kind suggestion.
The other thing that makes me wonder is the C++
code used for hls
which looks like specific for hls
and combines the hw
and sw
. What if I what to write my own layers and top function?
Can you give me some advises about your coding philosophy about c++
for hls and how you write them for hls
?
Thank you.
If you want to touch the HLS library and write your own layers etc., I recommend getting familiar with Vivado HLS first. You can follow the following tutorial as a starting point: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug871-vivado-high-level-synthesis-tutorial.pdf
I am closing this thread. If you have any specific questions later on, don't hesitate to contact me via email. I would be happy to help.
Thank you very much.@kaankara
Hi,
Create learning repository!
Thanks to your detailed
REAM.ME
, I have rebuilt the halfsqueezenet hw. And I have ahdmi overlay
by removing some many components of thebase overlay
.What I'm trying to do is that add the halfsqueezenet_0 IP to the hdmi overlay, so it's a live demo. But adding the
halfsqueezenet_0 IP
and theAXI DIrect Memory Access IP
, I got some error.Can you give me some advises about how you constructed your original block diagram, (because we rebuild your overlay according to the
procsys.tcl
which wasn't written by human~ ) and which IP I should add to get a live halfsqueezenet overlay?Thank you.