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free5G / free5GRAN

free5GRAN is an open-source 5G RAN stack. The current version includes a receiver which decodes MIB & SIB1 data. It also acts as a cell scanner. free5GRAN works in SA mode.
Apache License 2.0
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make error #16

Open moon657 opened 2 years ago

moon657 commented 2 years ago

Describe the bug I installed cmake 3.10 in my computer, but when I run make , there's something wrong

[100%] Building CXX object CMakeFiles/free5GRAN.dir/src/phy/phy.cpp.o /home/ubuntu/free5GRAN/src/phy/phy.cpp: In member function ‘int phy::init(free5GRAN::synchronization_object&, std::condition_variable&)’: /home/ubuntu/free5GRAN/src/phy/phy.cpp:373:49: sorry, unimplemented: non-trivial designated initializers not supported .shiftIndex = pci}}; ^ /home/ubuntu/free5GRAN/src/phy/phy.cpp:373:49: sorry, unimplemented: non-trivial designated initializers not supported /home/ubuntu/free5GRAN/src/phy/phy.cpp:373:49: sorry, unimplemented: non-trivial designated initializers not supported /home/ubuntu/free5GRAN/src/phy/phy.cpp:373:49: sorry, unimplemented: non-trivial designated initializers not supported /home/ubuntu/free5GRAN/src/phy/phy.cpp:373:49: sorry, unimplemented: non-trivial designated initializers not supported CMakeFiles/free5GRAN.dir/build.make:86: recipe for target 'CMakeFiles/free5GRAN.dir/src/phy/phy.cpp.o' failed make[2]: [CMakeFiles/free5GRAN.dir/src/phy/phy.cpp.o] Error 1 CMakeFiles/Makefile2:142: recipe for target 'CMakeFiles/free5GRAN.dir/all' failed make[1]: [CMakeFiles/free5GRAN.dir/all] Error 2 Makefile:129: recipe for target 'all' failed make: *** [all] Error 2

System:

nicolabui commented 2 years ago

you can rewrite the coreset0 initialization as

  free5GRAN::coreset coreset0;
  coreset0.controlResourceSetId = 0;
  coreset0.pdcch_DMRS_ScrambilngID = pci;
  coreset0.n_rb_coreset = pdcch_ss_mon_occ.n_rb_coreset;
  coreset0.duration = pdcch_ss_mon_occ.n_symb_coreset;
  coreset0.isMapped = true;
  coreset0.cce_REG_MappingType.reg_BundleSize = free5GRAN::NUMBER_REG_PER_CCE / pdcch_ss_mon_occ.n_symb_coreset;
  coreset0.cce_REG_MappingType.interleaverSize = 2;
  coreset0.cce_REG_MappingType.shiftIndex = pci;