fserre / SGen

SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs.
https://acl.inf.ethz.ch/research/hardware
GNU General Public License v3.0
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Mismatch between expected output and actual output when running testbench #10

Open xldeng-chn opened 7 months ago

xldeng-chn commented 7 months ago

Hi there, I was running the testbench for the design of 65536-point FFT with 256 streaming width. In terms of fixed-point representation, I set 8-bit integer and 8-bit fraction. Under this setting, I encountered the case that the actual output is mismatched with the expected output. I have seen the output of some points are really close to the expected output, while some have a large gap. I would like to know if this case is normal and if this is due to the precision loss of fixed-point representation. Below, I capture part of the testbench output. I would really appreciate a quick response.

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