search

fserre / SGen

SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs.
https://acl.inf.ethz.ch/research/hardware
GNU General Public License v3.0
21 stars 0 forks source link

Bad Coding Style #4

Closed Oxygen-Chu closed 3 years ago

Oxygen-Chu commented 3 years ago

Bad coding style of combinatorial logic using non-blocking assignment image

fserre commented 3 years ago

Hello, and thank you for your interest in SGen! The Verilog unparser was indeed using non-blocking assignments, and as the Xilinx toolchain didn't complain about it, this went completely unnoticed. Thank you a lot!

fserre commented 3 years ago

Designs on ACL website have been updated.