Open mithro opened 7 years ago
Currently we have a hack which uses the crt0 from MiSoC/LiteX libbase - https://github.com/upy-fpga/micropython/blob/master/litex/Makefile#L60-L61
As we are using newlib, we really should be using the crt0 from them.
In theory it should just be uncommenting these lines -> https://github.com/upy-fpga/micropython/blob/master/litex/litex.ld#L4-L7
However doing that causes the program to access memory location zero for some reason.
@shenki
Currently we have a hack which uses the crt0 from MiSoC/LiteX libbase - https://github.com/upy-fpga/micropython/blob/master/litex/Makefile#L60-L61
As we are using newlib, we really should be using the crt0 from them.
In theory it should just be uncommenting these lines -> https://github.com/upy-fpga/micropython/blob/master/litex/litex.ld#L4-L7
However doing that causes the program to access memory location zero for some reason.