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furrtek / DMG-CPU-Inside

Reverse-engineered schematics for DMG-CPU-B
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LYXE wrongly connected to LORU #44

Open msinger opened 3 years ago

msinger commented 3 years ago

On page 4, the first input of OR gate LYXE should be connected to the output of AND gate LAVY, not to LORU.

(Also, not really in issue, I noticed that the numbering of the inputs of LAVY is swapped: Input 1 is connected to CPU_WR2 and input 2 to FF46.)

msinger commented 3 years ago

Just realized LYXE is actually a RS latch. See #29. This means, the S input of latch LYXE is driven by LAVY, the R input of LYXE is driven by LOKO and the !Q output of LYXE goes into input 2 of LUPA. Q output is not connected.