furrtek / DMG-CPU-Inside

Reverse-engineered schematics for DMG-CPU-B
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T1 and T2 have inverting input buffers #54

Open msinger opened 2 years ago

msinger commented 2 years ago

The signals T1 and T2 that originate directly from their respective input pads should actually be marked as inverted. Just like the RESET signal is (but the other way around). So the signals that derive from them should be labeled something like this: t1t2_inverted Of course they need to be replaced all over the schematic as well. Yes, this means T1 and T2 need to be both 1 (not 0!) in order to reset the DFFs ADYK, AFUR, ALEF, APUK and AFER. And this means they are normally never reset at all! I have tested this extensively the last few days and documented everything here: http://iceboy.a-singer.de/doc/dmg_reset.html So everyone can safely experiment at home. :)