Closed carlosedp closed 3 years ago
To test this, I've installed my local Edalize branch supporting Libero, created a workspace, added my branch of blinky project and tried to build but no files were generated. Below the steps:
# Added my blinky local library (with this PR)
fusesoc library add --location ~/repos/fusesoc-blinky blinky-local ~/repos/fusesoc-blinky
# Built for Polarfire FPGA
fusesoc run --target=polarfireeval_es fusesoc:utils:blinky
INFO: Preparing fusesoc:utils:blinky:1.0
INFO: Setting up project
INFO: Set Libero tool option speed to default value -1
INFO: Set Libero tool option dievoltage to default value 1.0
INFO: Set Libero tool option range to default value IND
INFO: Set Libero tool option defiostd to default value LVCMOS 1.8V
fusesoc_utils_blinky_1.0.tcl
INFO: Running
# Got no files
❯ tree
.
└── fusesoc.conf
I expected the verilog files and the generated script should be created somewhere. Tips?
Well.... I would have expected that too :)
I can't think figure out why there's no build
directory created in your workspace. FuseSoc/Edalize should have created something like build/fusesoc_utils_blinky_0/polarfireeval_es-libero
where you script will be. I'll try your branch tomorrow and see if I can figure out what goes wrong. It obviously finds and runs your backend so it's super strange
Yes, I've added the "echo" command to my backend and it prints the script filename.
I tried it all from scratch but same happens, here's the full output:
❯ mkdir workspace
❯ cd workspace
❯ fusesoc library add blinky-local ~/repos/fusesoc-blinky
INFO: Interpreting sync-uri '/Users/cdepaula/repos/fusesoc-blinky' as location for local provider.
❯ cat fusesoc.conf
[library.blinky-local]
location = /Users/cdepaula/repos/fusesoc-blinky
sync-uri = /Users/cdepaula/repos/fusesoc-blinky
sync-type = local
auto-sync = true
❯ fusesoc core list
Available cores:
Core Cache status
================================================================================
fusesoc:utils:blinky:1.0 : local
❯ fusesoc core show fusesoc:utils:blinky
CORE INFO
Name: fusesoc:utils:blinky:1.0
Core root: /Users/cdepaula/repos/fusesoc-blinky
Targets:
AnalogMax : <No description>
ac701 : Xilinx Artix-7 FPGA AC701 Evaluation Kit
alhambra_II : Alhambra II iCE40-HX4K based open-source hardware board
apf27 : <No description>
apf51 : <No description>
arty_a7_35t : <No description>
arty_s7_50t : <No description>
arty_z7_20 : <No description>
cisco-hwic-3g-cdma : <No description>
colorlight_5a75b : <No description>
crosslink_nx_evn : CrossLink NX Evaluation Board
cyc1000 : <No description>
de0_nano : <No description>
de0_nanosoc : <No description>
de10_soc : <No description>
de1_soc_revF : <No description>
de5_net : <No description>
default : <No description>
ecp5_evn : ECP5 Evaluation Board
genesys2 : Digilent Genesys2 Board
ice40-hx1k_icestick : <No description>
ice40-hx8k_breakout : <No description>
ice40hx1k_evb : <No description>
kcu1500 : Kintex UltraScale KCU1500 Acceleration Development Kit
lx9_microboard : <No description>
machXO2_breakout : MachXO2 Breakout Board Evaluation Kit
machXO3_breakout : Lattice MachXO3LF Starter Kit LCMX03LF-6900C
max1000 : <No description>
mini_s7 : <No description>
nexys_a7 : <No description>
nexys_video : <No description>
opos6ul_sp : <No description>
orangecrab_r0.2 : OrangeCrab R0.2
pipistrello : <No description>
polarfireeval : Microsemi Polarfire Evaluation Kit
polarfireeval_es : Microsemi Polarfire Evaluation Kit (ES)
pynq_z2 : Pynq-Z2 Zynq Z7020 Evaluation Kit
sim : <No description>
soc_kit : <No description>
spartan_edge_accelerator_board : Spartan Edge Accelerator Board
tinyfpga_bx : <No description>
ulx3s_45 : Radiona ULX3S board with 45k FPGA
ulx3s_85 : Radiona ULX3S board with 85k FPGA
upduino2 : <No description>
xc6sl9_hseda_eda6.1 : <No description>
zcu102 : Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit
zcu106 : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit
zrtech_v2 : <No description>
zybo_z7-10 : Digilent Zybo Z7-10 SoC Kit
zybo_z7-20 : Digilent Zybo Z7-20 SoC Kit
❯ fusesoc run --target=polarfireeval_es fusesoc:utils:blinky
INFO: Preparing fusesoc:utils:blinky:1.0
INFO: Setting up project
INFO: Set Libero tool option speed to default value -1
INFO: Set Libero tool option dievoltage to default value 1.0
INFO: Set Libero tool option range to default value IND
INFO: Set Libero tool option defiostd to default value LVCMOS 1.8V
fusesoc_utils_blinky_1.0.tcl
INFO: Running
❯ ll
total 4.0K
-rw-r--r-- 1 cdepaula staff 155 Jan 26 19:31 fusesoc.conf
drwxr-xr-x 3 cdepaula staff 96 Jan 26 19:31 build/
❯ tree
.
└── fusesoc.conf
0 directories, 1 file
Weird :)
I've reinstalled some things and it's generated!
./build
└── fusesoc_utils_blinky_1.0
├── polarfireeval_es-libero
│ ├── fusesoc_utils_blinky_1.0.eda.yml
│ ├── fusesoc_utils_blinky_1_0-project.tcl
│ └── fusesoc_utils_blinky_1_0-run.tcl
└── src
└── fusesoc_utils_blinky_1.0
├── blinky.v
└── polarfireeval
├── blinky_polarfireeval.v
└── polarfireeval.pdc
Now I'm just adjusting some script generation things on both here and edalize. Will push changes soon!
Working perfectly with latest commits on edalize. Ready for review.
Many thanks for this and sorry for taking like a million years to review it
Add support for Microsemi Polarfire FPGA. This is still a WIP for review.
This PR depends on Libero support added to Edalize on https://github.com/olofk/edalize/pull/212.