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fusesoc / blinky

Example LED blinking project for your FPGA dev board of choice
MIT License
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Add support for EBAZ4205 'Development' Board #68

Closed kholia closed 3 years ago

kholia commented 3 years ago

This PR adds support for the EBAZ4205 'Development' Board.

References:

Usage:

fusesoc run --target=ebaz4205 fusesoc:utils:blinky

Tested with: Vivado 2021.1 running on Xubuntu 21.04

Notes:

The Zynq PL on this board doesn't have a reference clock without involving the Zynq PS.

To workaround this problem, the onboard 33MHz clock oscillator can be physically bridged to the PL clock input pin. To do this, solder a fine wire from R2340 (the clock output of X8) to the PL clock input on the pad for the missing R1372 near X5.

Credits: David Richards + the EBAZ4205 group on Telegram.

kholia commented 3 years ago

Pics or It Didn't Happen...

EBAZ4205 Clock Hacking

Logs:

...
Bitstream generation completed
INFO: [Common 17-206] Exiting Vivado at Wed Aug 11 18:41:10 2021...
INFO: Running
export HW_TARGET=; \
export JTAG_FREQ=; \
 vivado -quiet -nolog -notrace -mode batch -source fusesoc_utils_blinky_1.0_pgm.tcl -tclargs xc7z010clg400-1 fusesoc_utils_blinky_1.0.bit
FuseSoC Xilinx FPGA Programming Tool
====================================

INFO: Programming part xc7z010clg400-1 with bitstream fusesoc_utils_blinky_1.0.bit
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2021.1
  **** Build date : Jun 10 2021 at 20:11:57
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:

******** Xilinx cs_server v2021.1
  ****** Build date   : May 26 2021-23:02:33
    **** Build number : 2021.1.1622050353
      ** Copyright 2017-2021 Xilinx, Inc. All Rights Reserved.

INFO: Trying to use hardware target localhost:3121/xilinx_tcf/Digilent/210203859289A
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203859289A
INFO: Opened hardware target localhost:3121/xilinx_tcf/Digilent/210203859289A on try 1.
INFO: Found xc7z010clg400-1 as part of xc7z010_1.
INFO: Programming bitstream to device xc7z010_1 on target localhost:3121/xilinx_tcf/Digilent/210203859289A.
INFO: [Labtools 27-3164] End of startup status: HIGH
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210203859289A

INFO: SUCCESS! FPGA xc7z010clg400-1 successfully programmed with bitstream fusesoc_utils_blinky_1.0.bit.
olofk commented 3 years ago

That was a creative solution to the missing clock issue :) Thank you for your contribution. Picked and pushed