Ubuntu 20.04 doesn't build for `tang_nano`

I've been following these instructions and installed yosys manually using apt (apt install yosys -y) but get this when trying to build the project:

neil@NEIL-LEGION:~$ fusesoc run --target=tang_nano fusesoc:utils:blinky
WARNING: Unknown item board_device_index in section Ise
INFO: Preparing fusesoc:utils:blinky:1.1.1
INFO: Setting up project
INFO: Setting up project
INFO: Setting up project

INFO: Building
yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl'

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)

-- Running command `tcl edalize_yosys_template.tcl' --
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: ../src/fusesoc_utils_blinky_1.1.1/tang_nano/blinky.v
Parsing Verilog input from `../src/fusesoc_utils_blinky_1.1.1/tang_nano/blinky.v' to AST representation.
Storing AST representation for module `$abstract\top'.
Successfully finished Verilog frontend.

Syntax error in command `synth_gowin -json fusesoc_utils_blinky_1.1.1.json -top top':

    synth_gowin [options]

This command runs synthesis for Gowin FPGAs. This work is experimental.

    -top <module>
        use the specified module as top module (default='top')

    -vout <file>
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use BRAM cells in output netlist

    -nodram
        do not use distributed RAM cells in output netlist

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with -dff option

The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/gowin/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    bram:    (skip if -nobram)
        memory_bram -rules +/gowin/bram.txt
        techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v

    dram:    (skip if -nodram)
        memory_bram -rules +/gowin/dram.txt
        techmap -map +/gowin/drams_map.v
        determine_init

    fine:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/gowin/arith_map.v
        techmap -map +/techmap.v
        abc -dff    (only if -retime)

    map_ffs:
        dffsr2dff
        dff2dffs
        opt_clean
        dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
        techmap -map +/gowin/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        abc -lut 4
        clean

    map_cells:
        techmap -map +/gowin/cells_map.v
        hilomap -hicell VCC V -locell GND G
        iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O    (unless -noiopads)
        dffinit  -ff DFF Q INIT
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    vout:
        write_verilog -nodec -attr2comment -defparam -renameprefix gen <file-name>

ERROR: Command syntax error: Unknown option or option in arguments.
> synth_gowin -json fusesoc_utils_blinky_1.1.1.json -top top
>             ^
make: *** [Makefile:6: fusesoc_utils_blinky_1.1.1.json] Error 1
ERROR: Failed to build fusesoc:utils:blinky:1.1.1 : '['make']' exited with an error: 2
neil@NEIL-LEGION:~$

In looking into this, the yosys version installed by Aptitude on Ubuntu 20.04 (WSL on Windows 10) doesn't support the -json flag:

neil@NEIL-LEGION:~$ yosys -V
Yosys 0.9 (git sha1 1979e0b)
neil@NEIL-LEGION:~$ yosys --help

Usage: yosys [options] [<infile> [..]]

    -Q
        suppress printing of banner (copyright, disclaimer, version)

    -T
        suppress printing of footer (log hash, version, timing statistics)

    -q
        quiet operation. only write warnings and error messages to console
        use this option twice to also quiet warning messages

    -v <level>
        print log headers up to level <level> to the console. (this
        implies -q for everything except the 'End of script.' message.)

    -t
        annotate all log messages with a time stamp

    -d
        print more detailed timing stats at exit

    -l logfile
        write log messages to the specified file

    -L logfile
        like -l but open log file in line buffered mode

    -o outfile
        write the design to the specified file on exit

    -b backend
        use this backend for the output file specified on the command line

    -f frontend
        use the specified frontend for the input files on the command line

    -H
        print the command list

    -h command
        print the help message for the specified command

    -s scriptfile
        execute the commands in the script file

    -c tcl_scriptfile
        execute the commands in the tcl script file (see 'help tcl' for details)

    -p command
        execute the commands

    -m module_file
        load the specified module (aka plugin)

    -X
        enable tracing of core data structure changes. for debugging

    -M
        will slightly randomize allocated pointer addresses. for debugging

    -A
        will call abort() at the end of the script. for debugging

    -D <macro>[=<value>]
        set the specified Verilog define (via "read -define")

    -P <header_id>[:<filename>]
        dump the design when printing the specified log header to a file.
        yosys_dump_<header_id>.il is used as filename if none is specified.
        Use 'ALL' as <header_id> to dump at every header.

    -W regex
        print a warning for all log messages matching the regex.

    -w regex
        if a warning message matches the regex, it is printed as regular
        message instead.

    -e regex
        if a warning message matches the regex, it is printed as error
        message instead and the tool terminates with a nonzero return code.

    -E <depsfile>
        write a Makefile dependencies file with in- and output file names

    -g
        globally enable debug log messages

    -V
        print version information and exit

The option -S is an shortcut for calling the "synth" command, a default
script for transforming the Verilog input to a gate-level netlist. For example:

    yosys -o output.blif -S input.v

For more complex synthesis jobs it is recommended to use the read_* and write_*
commands in a script file instead of specifying input and output files on the
command line.

When no commands, script files or input files are specified on the command
line, yosys automatically enters the interactive command mode. Use the 'help'
command to get information on the individual commands.

neil@NEIL-LEGION:~$

I'm completely new to FPGA development and the associated toolchains, so could someone please help me figure out how I can build the project in my environment? Thanks!

fusesoc / blinky

Ubuntu 20.04 doesn't build for `tang_nano` #82