fvdhoef / vera-module

Versatile Embedded Retro Adapter
MIT License
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Sample the address and data bus earlier during writes. #19

Closed jburks closed 1 year ago

jburks commented 1 year ago

With this change, X16 is able to boot with a W65C816S at 8MHz. This fixes issue #15 .

A simple 2-entry "circular fifo" (if we can call it that) samples the address and data bus on the rising and falling edges of VERA's 25MHz clock. When bus_write is deasserted, the data latched into the oldest entry in the fifo is used instead of the data currently on the bus. This appears to be needed because the iCE40 has a 2-4 ns pad delay on many (all?) pads, and the extbus_wr_n signal is already delayed 8-10ns due to propagation delays of the 74xx logic and wire capacitance.

This also fixes an issue capturing A2 and A4 on small form factor X16 boards which have short, low capacitance address wires. For reasons I only partially understand, this only affects A2 and A4. (The issue can be fixed on these boards by adding a small load capacitor, 20-30pF, to A2 and A4.)

I'm not sure I am confident with the strategy used with this fix, but of the 10-12 different methods of working around this problem that I came up with and tested, this is the only one that survived every stress test without failure on both 65C02 and 65C816.