VBlank IRQ generation is missing every odd frames in interlaced modes

[akumanatt]

As seen here, the signal should be generated on both even frames and odd frames, giving ~60Hz rate: https://github.com/fvdhoef/vera-module/blob/8714ce16898da7e1431083bf62029a613355361d/fpga/source/video/video_composite.v#L121 However, since vcnt counts twice per line, h_last is only true when vcnt is odd. This can be fixed by replacing h_last with h_half_line_last just like in the field toggling logic.

Here is a measurement confirming the bug:

[jburks]

A brief clarification of the trace above. The yellow "VSYN" signal was obtained with the probe on the HSYNC pin. It is the composite sync signal and should have just been labeled "SYNC".