Open fyquah opened 2 years ago
Hi @fyquah
How would that approach be different from "Tri_mode_ethernet" approach? Also, by the module currently sitting there, are you referring to https://github.com/fyquah/hardcaml_arty/blob/master/examples/blinker/ips/hardcaml_arty_tri_mode_ethernet_mac_0/hardcaml_arty_tri_mode_ethernet_mac_0.xci?
On the same topic, I see that Ethernet section of the README is incomplete, could you share a basic example of using Ethernet with hardcaml on an Arty A7 board?
Ed
Xilinx web pack does come with a free ethernet mac. The mac supports 100MB and 10MB ethernet, which is sufficient to get something working.
Implementing will comprises of a few steps: