Closed hbina closed 6 years ago
it must be related the your code, let me know which line failed? or press F12, and open the console.
The same for me, however this time it gives out more code than it is supposed to and it is still not complete. I tried a few things and this is what I found to be the issue.
It only happens though when you use package bodies. If you only use packages, everything inside them is formatted correctly. The following code is not formatted correctly.
PACKAGE BODY A_MAIN_ASYNC_PKG IS
FUNCTION log2(
a : INTEGER
) RETURN INTEGER IS
VARIABLE temp : INTEGER := a;
VARIABLE temp2 : BOOLEAN := false;
VARIABLE result : INTEGER := 0;
BEGIN
RETURN result;
END FUNCTION;
END A_MAIN_ASYNC_PKG;
Could you please provide more information (example input, expected output), so that I can reproduce this bug. I need to know two things 1) under what circumstances it does not give complete output 2) what is the expected format for packages
Ok, I've managed to find the issue. There are 2 issues actually.
Here is the ORIGINAL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- use ieee.std_logic_arith.all;
package A_MAIN_ASYNC_PKG is
procedure wait_until(
signal a : in data_status;
b : data_status
);
--=================================--
end package;
package body A_MAIN_ASYNC_PKG is
-------------------------------------
impure function delay(
lowerLimit : integer;
upperLimit : integer
) return time is
variable result : time;
variable randNumber: real;
begin
result := 2ps;
return result;
if (lowerLimit >= upperLimit) then
result := lowerLimit * (time_resolution);
else
result := (integer(
(randNumber *
real(upperLimit - lowerLimit) +
real(lowerLimit)) *
1000.0
) + 2) * time_resolution; -- !!!!COMMENT!!!!!
end if;
return result;
end function;
end A_MAIN_ASYNC_PKG;
and this is how it gets formatted:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- use ieee.std_logic_arith.all;
package A_MAIN_ASYNC_PKG is
procedure wait_until(
signal a : in data_status;
b : data_status
);
--=================================--
end package;
package body A_MAIN_ASYNC_PKG is
-------------------------------------
impure function delay(
lowerLimit : integer;
upperLimit : integer
) return time is
variable result : time;
variable randNumber : real;
begin
result := 2ps;
return result;
if (lowerLimit >= upperLimit) then
result := lowerLimit * (time_resolution);
else
result := (integer(
(randNumber *
real(upperLimit - lowerLimit) +
real(lowerLimit)) *
1000.0
-- !!!!COMMENT!!!!!
) + 2) * time_resolution;
end if;
return result;
end function;
The lines after "impure function" are not indented correctly. Also, the "end package" line is missing. Also, note that the comment has been moved one line above for some reason.
I hope this explains it all.
Thanks, I've updated the code based on your description. please check if the issues are fixed.
If so, feel free to close the bug.
If not, please let me know what can be improved.
Ok, the missing package body is ok now, however, there is an issue with the indentation of the functions/procedures in the "package" declaration. Here is the original code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- use ieee.std_logic_arith.all;
package A_MAIN_ASYNC_PKG is
-- Functions
-- ============= MATHS ======================--
function log2(
a : integer
) return integer;
function min_size(
a : integer;
b : integer
) return integer;
function max_size(
a : integer;
b : integer
) return integer;
function parity_check(
a : data_qword;
b : positive
-- true for even, false for odd
) return boolean;
-- function inc_std_logic_vector(
-- a : std_logic_vector;
-- inc_size : integer
-- -- use up to 32 bits
-- -- MSB on the left ALWAYS
-- ) return std_logic_vector;
-- ============= MISC =======================--
-- function check_for_jump(
-- a : data_bit_vector
-- ) return boolean;
--
-- function get_jump_address(
-- a : data_bit_vector;
-- address_size : integer
-- ) return data_bit_vector;
-- ============= CONVERSIONS =================--
function to_integer(
a : data_bit_vector
) return integer;
-- function to_integer(
-- a : data_qword;
-- b : positive
-- ) return integer;
function to_data_bit_vector(
intToConvert : integer;
arraySize : integer
) return data_bit_vector;
function to_data_bit_vector(
a : std_logic_vector
) return data_bit_vector;
function to_data_bit_vector(
a : string
) return data_bit_vector;
function to_data_bit_vector(
a : ack_bit_vector
) return data_bit_vector;
function to_data_bit_vector(
a : data_qword;
b : positive
) return data_bit_vector;
function to_std_logic_vector(
a : data_bit_vector
) return std_logic_vector;
function to_ack_bit_vector(
a : data_bit_vector
) return ack_bit_vector ;
function equal(
a : data_bit_vector;
b : data_bit_vector
) return boolean;
function all_ones(
a : data_bit_vector
) return boolean;
function all_ones(
a : data_qword;
b : positive
) return boolean;
function all_zeros(
a : data_qword;
b : positive
) return boolean;
function get_data_status(
a : data_bit_vector
) return data_status;
function get_data_status (
a : data_size_selector
) return data_status;
end package;
and here is how it gets formatted:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- use ieee.std_logic_arith.all;
package A_MAIN_ASYNC_PKG is
-- Functions
-- ============= MATHS ======================--
function log2(
a : integer
) return integer;
function min_size(
a : integer;
b : integer
) return integer;
function max_size(
a : integer;
b : integer
) return integer;
function parity_check(
a : data_qword;
b : positive
-- true for even, false for odd
) return boolean;
-- function inc_std_logic_vector(
-- a : std_logic_vector;
-- inc_size : integer
-- -- use up to 32 bits
-- -- MSB on the left ALWAYS
-- ) return std_logic_vector;
-- ============= MISC =======================--
-- function check_for_jump(
-- a : data_bit_vector
-- ) return boolean;
--
-- function get_jump_address(
-- a : data_bit_vector;
-- address_size : integer
-- ) return data_bit_vector;
-- ============= CONVERSIONS =================--
function to_integer(
a : data_bit_vector
) return integer;
-- function to_integer(
-- a : data_qword;
-- b : positive
-- ) return integer;
function to_data_bit_vector(
intToConvert : integer;
arraySize : integer
) return data_bit_vector;
function to_data_bit_vector(
a : std_logic_vector
) return data_bit_vector;
function to_data_bit_vector(
a : string
) return data_bit_vector;
function to_data_bit_vector(
a : ack_bit_vector
) return data_bit_vector;
function to_data_bit_vector(
a : data_qword;
b : positive
) return data_bit_vector;
function to_std_logic_vector(
a : data_bit_vector
) return std_logic_vector;
function to_ack_bit_vector(
a : data_bit_vector
) return ack_bit_vector;
function equal(
a : data_bit_vector;
b : data_bit_vector
) return boolean;
function all_ones(
a : data_bit_vector
) return boolean;
function all_ones(
a : data_qword;
b : positive
) return boolean;
function all_zeros(
a : data_qword;
b : positive
) return boolean;
function get_data_status(
a : data_bit_vector
) return data_status;
function get_data_status (
a : data_size_selector
) return data_status;
end package;
as you can see there is a tab added after each new function/procedure declaration.
fixed
All working. Ok to close the issue.
I have a top level vhdl with 350~ lines but it will only return ~300 or so.