g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
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Multi-line constant and signal are not indented #19

Closed ryoi6 closed 3 years ago

ryoi6 commented 5 years ago

Report a bug

If constant is multi-line, constant is not indented. signal is also the same.

Input

type type_sig is record
    a : std_logic;
    b : std_logic;
end record;

constant : sig_init : type_sig := (
    a => '0',
    b => '0'
);

signal test_sig : type_sig := (
    a => '0',
    b => '0'
);

Expected Behavior

type type_sig is record
    a : std_logic;
    b : std_logic;
end record;

constant : sig_init : type_sig := (
    a => '0',
    b => '0'
);

signal test_sig : type_sig := (
    a => '0',
    b => '0'
);

Actual Behavior

type type_sig is record
    a : std_logic;
    b : std_logic;
end record;

constant : sig_init : type_sig := (
a => '0',
b => '0'
);

signal test_sig : type_sig := (
a => '0',
b => '0'
);
are512 commented 4 years ago

This issue is now closed

ryoi6 commented 3 years ago

I'll close this as it's fixed. Thank you!