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g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
51 stars 20 forks source link

Request to align signal types after IO #24

Closed are512 closed 3 years ago

are512 commented 4 years ago

Request a new feature

As a user, I want to...

Be able to align the signal types after IO's

Example Input:

SIGNAL sig_1 : IN std_ulogic;
SIGNAL sig_2 : OUT std_ulogic;
SIGNAL sig_3 : INOUT std_ulogic;

Example Output:

SIGNAL sig_1 : IN    std_ulogic;
SIGNAL sig_2 : OUT   std_ulogic;
SIGNAL sig_3 : INOUT std_ulogic;
g2384 commented 4 years ago

Good one! I don't have enery to implement this yet. :(

g2384 commented 3 years ago

Thanks for your contribution. I've extended it to cover in, out, buffer, and inout. This issue is fixed now.