g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
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Alignment of multiple assignments containing <= comparisons #30

Open raiker opened 4 years ago

raiker commented 4 years ago

Report a bug

Input

(align signs in all places selected)

ringbuffer_full <= '1' when write_ptr + 1 = wr_read_ptr else '0';
ringbuffer_almost_empty  <= '1' when ringbuffer_rd_count <= 1 else '0';

Expected Behavior

The two assignments should be aligned at the first "<=", eg

ringbuffer_full          <= '1' when write_ptr + 1 = wr_read_ptr else '0';
ringbuffer_almost_empty  <= '1' when ringbuffer_rd_count <= 1 else '0';

Actual Behavior

It appears that the 'less than or equal' to in the conditional expression is confusing the alignment, and the output I get is

ringbuffer_full <= '1' when write_ptr + 1 = wr_read_ptr else '0';
ringbuffer_almost_empty <= '1' when ringbuffer_rd_count <= 1 else '0';

If I replace the "<=" in the assignment with ">=", everything works correctly:

ringbuffer_full         <= '1' when write_ptr + 1 = wr_read_ptr else '0';
ringbuffer_almost_empty <= '1' when ringbuffer_rd_count >= 1 else '0';

Thanks

g2384 commented 4 years ago

this is tricky, thanks for your report.

raiker commented 4 years ago

Yes, it looks tricky. It might be sufficient to align the first "<=" on each line, though. A similar thing happens with alignment in entity instantiation signal connection lists:

ACIN => (others => '0'),
BCIN => (others => '0'),
CARRYCASCIN    => '0',

where the second "=>" in the array expression confuses the alignment.

NINI1988 commented 4 years ago

The same problems happens when <= comparision is used in if statements.

IF (inputA <= 100) AND (inputB <= 5000) THEN
    valueA        <= 1;
    valueB        <= 2;
ELSIF (inputA <= 100) AND (inputB > 5000) THEN
    valueB        <= 3;
ELSE
    valueB <= 4;
END IF;