Bad Alignment for "when" and "if" in same line

[el-coder-sb]

I think there is a problem if "when" and "if" are in same line. I´m using VHDLFormatter with the cli fork of @raczben with added signAlignSettings(true, false, "global", ["PORT", "GENERIC"]);.

Input

txSTATE_FSM: process (Reset_s, CLk_1MHz, Clk_2_s, nLoad_Reg_s)
    begin
      IF (Reset_s = '1') then
        txSTATE <= D_shift_in;
      elsif (CLk_1MHz='1' and CLk_1MHz'event) then
        case txSTATE is
          when  D_out_ready    =>
                                if (Clk_2_s='1') then          -- wait
                                        txSTATE  <=  D_shift;
                                      --  txSTATE  <=  D_shift_out;
                                      end if;
          when  D_shift        =>     if (Clk_2_s='1') then          -- data
                                        txSTATE  <=  D_shift;
                                      else if (nLoad_Reg_s='1') then
                                        txSTATE  <=  D_shift_in;
                                      end if;

          when  D_shift_in     =>     if (nLoad_Reg_s='1') then        -- data
                                        txSTATE  <=  D_shift_out;
                                        ok_reset <= '1';
                                      end if;
          when  D_shift_in_ok  =>     null;
          when  D_out_D        =>     null;
        end case;
      end if;
    end process;

Expected Behavior

    txSTATE_FSM : process (Reset_s, CLk_1MHz, Clk_2_s, nLoad_Reg_s)
    begin
        if (Reset_s = '1') then
            txSTATE <= D_shift_in;
        elsif (CLk_1MHz = '1' and CLk_1MHz'event) then
            case txSTATE is
                when D_out_ready =>
                    if (Clk_2_s = '1') then -- wait
                        txSTATE <= D_shift;
                        --  txSTATE  <=  D_shift_out;
                    end if;
                when D_shift => if (Clk_2_s = '1') then -- data
                        txSTATE <= D_shift;
                    else if (nLoad_Reg_s = '1') then
                        txSTATE <= D_shift_in;
                    end if;

                when D_shift_in => if (nLoad_Reg_s = '1') then -- data
                        txSTATE <= D_shift_out;
                        ok_reset <= '1';
                    end if;
                when D_shift_in_ok => null;
                when D_out_D => null;
            end case;
        end if;
    end process;

Actual Behavior

    txSTATE_FSM : process (Reset_s, CLk_1MHz, Clk_2_s, nLoad_Reg_s)
    begin
        if (Reset_s = '1') then
            txSTATE <= D_shift_in;
        elsif (CLk_1MHz = '1' and CLk_1MHz'event) then
            case txSTATE is
                when D_out_ready =>
                    if (Clk_2_s = '1') then -- wait
                        txSTATE <= D_shift;
                        --  txSTATE  <=  D_shift_out;
                    end if;
                when D_shift => if (Clk_2_s = '1') then -- data
                    txSTATE <= D_shift;
                else if (nLoad_Reg_s = '1') then
                    txSTATE <= D_shift_in;
            end if;

            when D_shift_in => if (nLoad_Reg_s = '1') then -- data
            txSTATE <= D_shift_out;
            ok_reset <= '1';
        end if;
        when D_shift_in_ok => null;
        when D_out_D => null;
    end case;
end if;
end process;